We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34201

VCS - GTXE1 primitive fails to simulate in VCS


When I applyresets to the GTXE1s, the"RESETDONE" signal does not assert. Some internal signals (such as delay_RXUSRCLK and delay_RXUSRCLK2) also unexpectedly appear as 'X'


This issue has been found while performing a timing simulation on a Virtex-6 design using GTXE1 primitives using VCS-MX D-2009.12. Synopsys has been informed of this issue so it is addressed in a future release of the simulator.

To work around this issue, set thevcs option "-nohsopt". This switch disables an optimization algorithm that causes the issue.

For additional help on this topic, please contact Xilinx Technical Support (http://www.xilinx.com/support/clearexpress/websupport.htm)

AR# 34201
Date Created 01/21/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4