We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34203

11.x ChipScope - IBERT - Spartan-6, Virtex-5, Virtex-6 - PCS loopback results in an increasing error count


When I set my GT to near-end PCS loopback, I see the bit error rate increasing. Is there an issue with my device?


This is a result of clock settings in the core. As a work-around, use PMA near-end loopback. Alternatively, you can change the Loopback mode to Near-End PMA and then change back to Near-End PCS. Reset Error count and note that no errors occur.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33839 Spartan-6 FPGA SP605 - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 34203
Date Created 01/29/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LXT
  • Virtex-5 TXT
  • Virtex-5 SXT
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-6 CXT
  • Less
Boards & Kits
  • Spartan-6 FPGA SP605 Evaluation Kit
  • Spartan-6 FPGA Connectivity Kit
  • Spartan-6 FPGA Embedded Kit