There are two deviations from the standard Wizard generation flow that need to be taken note of to generate a wrapper for 6.6Gb/s:
1) In the Virtex-6 FPGA GTX Transceiver Wizard itself, when selecting a line rate, simply select 6.5Gb/s and a reference clock rate that is just lower than what is expected to be used for 6.6Gb/s. This will ensure that all the settings generated by the Wizard are correct for the high line rate, including the PLL divider settings.
2) The example UCF generated by the wizard will have timing constraints that are slightly too low for the target speeds. Update the reference clock period constraint to match the period of the expected reference clock and the TXUSRCLK2 constraint to be inline with the formulas in the FPGA RX and TX Interface sections of the Virtex-6 FPGA GTX Transceiver User's Guide: