Design Assistant

Xilinx MIG Solution Center - Design Assistant

Select the appropriate Design Assistant below to learn more about designing with a MIG core or to find help on debugging an issue that you are currently encountering. The MIG Design Assistants walk you through the recommend design flow for MIG while debugging commonly encountered issues such as simulation issues, calibration failures, and data errors. The Design Assistants provide useful design and troubleshooting information, but also point you to the exact documentation you need to read to help you design efficiently with MIG.

NOTE: This answer record is a part of the Xilinx MIG Virtex-6 and Spartan-6 Solution Center (Xilinx Answer 34243). The Xilinx MIG Virtex-6 and Spartan-6 Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Virtex-6 and Spartan-6 Solution Center to guide you to the right information.

(Xilinx Answer 51313) MIG 7 Series Design Assistant
(Xilinx Answer 34266) MIG Virtex-6 Design Assistant
(Xilinx Answer 37496) MIG Spartan-6 Design Assistant

Answer Number	Answer Title	Version Found	Version Resolved
34266	Xilinx Virtex-6 MIG Solution Center - Design Assistant	N/A	N/A
37496	Xilinx Spartan-6 MIG Solution Center - Design Assistant	N/A	N/A
51313	Xilinx MIG 7 Series Solution Center - Design Assistant	N/A	N/A

Documentation

Xilinx MIG Solution Center - Documentation

Please refer to the following documentation when using MIG.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

7 Series Memory Interface Solutions

Please visit the 7 Series MIG Documentation Center, which includes:

• UG586 - 7 Series FPGAs Memory Interface Solutions User Guide
• DS176 - 7 Series FPGAs Memory Interface Solutions Data Sheet
• Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
• MIG 7 Series - Release Notes and Known Issues

Additional Resources:
WP383 - Achieving High Performance DDR3 Data Rates in Virtex-7 and Kintex-7 FPGAs

7 Series FPGAs Memory Interface Performance Specifications
Please visit the 7 Series FPGAs Data Sheets Documentation Center, which includes:

• Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
• Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
• Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Spartan-6 and Virtex-6 Memory Interface Solutions

Please visit the MIG Virtex-6 and Spartan-6 Documentation Center, which includes:

• UG406 - Virtex-6 Memory Interface Solutions User Guide
• DS186 - Virtex-6 Memory Interface Solutions Data Sheet
• UG388 - Spartan-6 Memory Controller User Guide
• UG416 - Spartan-6 Memory Interface Solutions User Guide
• Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
• MIG Virtex-6 and Spartan-6 - Release Notes and Known Issues

Additional Resources:
XAPP868 - Interfacing QDR II SRAM Devices with Virtex-6 FPGAs

Memory Interface Board/Pinout Design

Each MIG User Guide includes sections dedicated to Memory Interface Board/Pinout Guidelines. Please visit the above noted User Guide specific to your MIG design.

Virtex-5 Memory Interface Solutions

• UG086 - Memory Interface Solutions User Guide
• XAPP858 - High-Performance DDR2 SDRAM Interface in Virtex-5 Devices
• XAPP853 - QDR II SRAM Interface for Virtex-5 Devices
• XAPP852 - RLDRAM II Memory Interface for Virtex-5 FPGAs
• XAPP851 - DDR SDRAM Controller Using Virtex-5 FPGA Devices
• WP260 - Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface Generator

Spartan-3 Generation Memory Interface Solutions

• UG086 - Memory Interface Solutions User Guide
• XAPP454 - DDR2 SDRAM Interface for Spartan-3 Generation FPGAs
• XAPP768c - Interfacing Spartan3 Devices With 166 MHz or 333 Mb/s DDR SDRAM Memories
• XAPP458 - Implementing DDR2-400 Memory Interfaces in Spartan-3A FPGAs
• WP260 - Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface Generator

Virtex-4 Memory Interface Solutions

• UG086 - Memory Interface Solutions User Guide
• XAPP721 - High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES
• XAPP723 - DDR2 Controller (267 MHz and Above) Using Virtex-4 Devices
• XAPP701 - DDR2 SDRAM Physical Layer Using Direct-Clocking Technique
• XAPP702 - DDR2 Controller Using Virtex-4 Devices
• XAPP709 - DDR SDRAM Controller Using Virtex-4 FPGA Devices
• XAPP703 - QDR II SRAM Interface for Virtex-4 Devices
• XAPP710 - Synthesizable CIO DDR RLDRAM II Controller for Virtex-4 FPGAs

Revision History
11/15/11- Updated to point to MIG documentation pages
4/6/11 - Added WP383 and XAPP868
3/1/11 - Added 7 Series Memory Interface Documentation

Design Advisories

Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

For a list of all current Release Notes and Known Issues for Xilinx Solutions for MIG, please refer to the IP Release Notes Guide (XTP025):
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

For general design and troubleshooting information on MIG, please refer to the Xilinx MIG Solution Center at: (Xilinx Answer 34243).

7 Series DDR3 MIG
01/28/2013 - (Xilinx Answer 53860) Design Advisory for MIG 7 Series DDR3 - All CK clock pins must to be in the same byte lane/group. Validating Dual Rank Pin-Outs Required.
01/28/2013 - (Xilinx Answer 53919) Design Advisory for MIG 7 Series v1.8 RLDRAM II - Pinout violation not detected in "Fixed Pin Out" mode or "Verify Pin Changes and Update Design" flow.
01/21/2013 - (Xilinx Answer 53607) Design Advisory for MIG 7 Series QDRII+ - Inferred latches cause write calibration failures. Work-around required.
01/07/2013 - (Xilinx Answer 53420) Design Advisory for MIG 7 Series DDR3/DDR2 - Required calibration patch for v1.7 and v1.8
12/10/2012 - (Xilinx Answer 53053) Design Advisory MIG 7 Series QDRII+ - Read calibration failures can occur when CPT_CLK_CQ_ONLY=FALSE
10/24/2012 - (Xilinx Answer 52573) Design Advisory MIG 7 Series DDR3 - Issue with OCLKDELAY calibration causes write DQS to be aligned to DQ with potential calibration failures
10/24/2012 - (Xilinx Answer 51687) Design Advisory MIG 7 Series DDR3/DDR2 - Temperature monitor calibration using XADC block added to all DDR3/DDR2 designs in v1.7 (ISE 14.3/Vivado 2012.3)
08/20/2012 - (Xilinx Answer 51296) Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases
08/06/2012 - (Xilinx Answer 50461) Design Advisory MIG 7 Series v1.6 - Calibration updates for all interfaces
05/14/2012 - (Xilinx Answer 47043) Design Advisory MIG 7 Series - Addition of MMCM to clocking structure starting with v1.5 (available with ISE Design Suite 14.1)
03/12/2012 - (Xilinx Answer 45653) Design Advisory MIG 7 Series v1.4 DDR2/DDR3 - Calibration Update. Revised patch from 2/23/2012. Required for designs targeting Initial Engineering Sample devices.
02/23/2012 - (Xilinx Answer 45653) Design Advisory MIG 7 Series v1.4 DDR2/DDR3 - Calibration Update
01/10/2012 - (Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified
05/05/2011 - (Xilinx Answer 42036) 7 Series MIG DDR3 - Internal/External Vref Guidelines
05/02/2011 - (Xilinx Answer 41981) MIG 7 Series 1.1 DDR3 SDRAM - Addr/Cntrl pins should be limited to a single bank
04/11/2011 - (Xilinx Answer 40876) MIG 7 Series 1.1 DDR3 SDRAM - MIG allows setting memory frequencies above data sheet specifications
04/11/2001 - OBSOLETE (Xilinx Answer 41351) MIG 7 Series 1.1 DDR3 SDRAM - CKE and ODT Pin Placement Guidelines

Spartan-6 FPGA MCB
04/25/2011 - (Xilinx Answer 41822) MIG v3.7 Spartan-6 MCB - Certain User Port Configurations do not work for VHDL designs
04/18/2011 - (Xilinx Answer 41520) Spartan-6 MCB Design Advisory - Removal of VCCINT restrictions to reach maximum DDR3 data rates
11/09/2010 - (Xilinx Answer 36291) MIG, MPMC, Spartan-6 MCB - Memory failures occur on initial configuration.
06/14/2010 - (Xilinx Answer 35978) MIG Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs.
06/14/2010 - (Xilinx Answer 35976) MIG Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality - SW / IP update required.
06/14/2010 - (Xilinx Answer 35818) Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 and DDR3 interfaces.
02/08/2010 - (Xilinx Answer 34165) MIG v3.3, Spartan-6 FPGA MCB - Incorrect port connection causes Continuous DQS Tuning to behave incorrectly - Manual modification required.
02/08/2010 - (Xilinx Answer 34046) MIG v3.3, Spartan-6 FPGA LPDDR - Calibrated and Un-Calibrated Input Termination features not supported.
02/08/2010 - (Xilinx Answer 34055) MIG v3.3, Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?
02/08/2010 - (Xilinx Answer 34137) MIG v3.3, Spartan-6 FPGA LPDDR - Drive strength selected in MIG is not properly set in the output design.
02/08/2010 - (Xilinx Answer 34089) MIG v3.3, Spartan-6 FPGA MCB - Some bits of the MCB address bus (mcbx_dram_addr) may violate the input hold time (tIH) specification of the memory device.
09/23/2009 - (Xilinx Answer 33358) Spartan-6 FPGA MCB - Data Mask cannot be disabled and the UDM and LDM pins cannot be used as General Purpose I/O (GPIO).

Virtex-6 DDR2/DDR3 MIG
03/9/2010 - (Xilinx Answer 34204) MIG v3.0-3.3, Virtex-6 FPGA DDR3/DDR2 - Read Leveling Stage 2 fails in hardware due to OCB Monitor issue.
02/8/2010 - (Xilinx Answer 33995) MIG 3.3, Virtex-6 FPGA DDR3 - Write Leveling does not succeed and calibration fails due to IDELAYCTRL not being automatically inferred by the software.
02/8/2010 - (Xilinx Answer 34094) MIG v3.3, Virtex-6 FPGA DDR2/DDR3- MMCM CLKFBOUT_MULT_F= 4 not valid, manual modification required

To update your Xilinx Alert Notification Preferences, please go to:
http://www.xilinx.com/support/myalerts

Revision History
01/28/2013 - Added 53919 and 53860
01/21/2013 - Added 53607
01/07/2013 - Added 53420
12/10/2012 - Added 53053
10/24/2012 - Added 51687 and 52573
08/20/2012 - Added 51296
08/06/2012 - Added 50461
05/14/2012 - Added 47043
03/12/2012 - Added updated patch for 45653
02/23/2012 - Added 45653
01/10/2012 - Added 45633
05/05/2011 - Updated 7 Series DDR3 MIG to include 42036
05/02/2011 - Updated 7 Series DDR3 MIG to include 41981
04/18/2011 - Updated Spartan-6 list to include 41520
04/11/2011 - Added 7 Series and included 40876 and 41351
11/09/2010 - Updated Spartan-6 list to include 36291
06/14/2010 - Updated Spartan-6 list to include 35978, 35976, and 35818
03/09/2010 - Updated list to include 34204
02/08/2009 - Updated list to include 34165, 34046, 34055, 34137, 34089, 33995, and 34094
09/28/2009 - Initial Release; added 33358

Answer Number	Answer Title	Version Found	Version Resolved
45633	Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified	N/A	N/A
53053	Design Advisory for MIG 7 Series QDRII+ - Read calibration failures can occur when CPT_CLK_CQ_ONLY=FALSE	N/A	N/A
51296	Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases	N/A	N/A
41981	MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Addr/Cntrl Pins Should be Limited to a Single Bank	N/A	N/A
41822	MIG v3.7 Spartan-6 MCB - Certain User Port Configurations do not work for VHDL designs	N/A	N/A
35976	Design Advisory for MIG, MPMC Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality (software/IP update required)	N/A	N/A
47043	Design Advisory MIG 7 Series - Addition of MMCM to Clocking Structure Starting with v1.5 (available with ISE Design Suite 14.1)	N/A	N/A
41520	Design Advisory for Spartan-6 MCB - Removal of VCCINT Restrictions to Reach Maximum DDR3 Data Rates	N/A	N/A
35978	Design Advisory for MIG, MPMC Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs	N/A	N/A
35818	Design Advisory for Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 Interfaces	N/A	N/A
34204	MIG v3.0-3.3, Virtex-6 DDR3/DDR2 - Read Leveling Stage 2 fails in hardware due to OCB Monitor issue	N/A	N/A
50461	Design Advisory MIG 7 Series v1.6 - Calibration updates for all interfaces	N/A	N/A

Top Issues

Xilinx MIG Solution Center - Top Issues

The following answer records cover current known issues as well as commonly asked questions related to MIG.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Please select the appropriate MIG product below:

(Xilinx Answer 46227) MIG 7 Series Top Issues
(Xilinx Answer 34265) MIG Virtex-6 and Spartan-6 Top Issues

Answer Number	Answer Title	Version Found	Version Resolved
34265	MIG Solution Center - MIG Virtex-6 and Spartan-6 Top Issues	N/A	N/A
46227	MIG 7 Series Solution Center - Top Issues	N/A	N/A

Feed Back