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AR# 34245

BUFR resource in Virtex-6 FPGA


The regional clock buffer (BUFR) is a clock buffer available in Virtex-6 devices. BUFRs drive clock signals to a dedicated clock net within a clock region, independent from the global clock tree.


Each I/O column supports regional clock buffers. There are up to four I/O columns in a device with two inner columns (center left and right) and up to two outer left and right columns. The availability of the outer columns are device dependant, while the inner columns are always present. The Virtex-6 architecture, therefore, can have up to four BUFRs per region withtwo driving from the inner columns out (always present), and two BUFRs per region driving from the outer I/O columns in (when present).

The current version of the Virtex-6 FPGA Clocking Resource Guide states that thereareup to eight BUFRs per region. This will be changed in a newer version of the guide.
AR# 34245
Date 02/28/2013
Status Active
Type General Article
  • Virtex-6 LX
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
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