The following is the datasheet section from the timing report.
The design is a source-synchronous design.
The difference between the max delay (slowest corner) and the min delay (fastest corner) is nearly 4ns, although the skew between the output pads under either slow or fast condition is very small.
Is the delay difference (~4ns) between the Max and Min delays the maximum skew of the source synchronous interface?
For V6/S6 and newer devices, multicorner analysis is done.
This finds the max (speed grade) and the min (-0 speed grade) delays during the analysis of a design.
Because the timing analysis tools have both the min and the max available, it was requested to add both to the datasheet section of the timing report.
This provides the user with the worst-case clock to out and the best-case clock to out.
Since a given device will not have either extreme, you should not compare the worst-case to the best-case.
The worst-case values are used to ensure a setup requirement on the downstream device is met and the best-case values are used to ensure a hold requirement is met.
In a Source Synchronous design, the bus skew is more critical than the actual delays.
Traditionally, the clock is forwarded with the data in a Source Synchronous design, and the bus skew informs the user of the variation between the clock and the data bus, assuming the forwarded clock is in the same OFFSET OUT analysis.