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AR# 34263 Xilinx MIG Solution Center - Documentation

Description

Please refer to the following documentation when using MIG.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

7 Series Memory Interface Solutions

Please visit the 7 Series MIG Documentation Center, which includes:

  • UG586 - 7 Series FPGAs Memory Interface Solutions User Guide
  • DS176 - 7 Series FPGAs Memory Interface Solutions Data Sheet
  • Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
  • MIG 7 Series - Release Notes and Known Issues

Additional Resources:
WP383 - Achieving High Performance DDR3 Data Rates in Virtex-7 and Kintex-7 FPGAs

7 Series FPGAs Memory Interface Performance Specifications
Please visit the 7 Series FPGAs Data Sheets Documentation Center, which includes:

  • Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
  • Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
  • Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Spartan-6 and Virtex-6 Memory Interface Solutions

Please visit the MIG Virtex-6 and Spartan-6 Documentation Center, which includes:

  • UG406 - Virtex-6 Memory Interface Solutions User Guide
  • DS186 - Virtex-6 Memory Interface Solutions Data Sheet
  • UG388 - Spartan-6 Memory Controller User Guide
  • UG416 - Spartan-6 Memory Interface Solutions User Guide
  • Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
  • MIG Virtex-6 and Spartan-6 - Release Notes and Known Issues
Additional Resources:
XAPP868 - Interfacing QDR II SRAM Devices with Virtex-6 FPGAs

Memory Interface Board/Pinout Design

Each MIG User Guide includes sections dedicated to Memory Interface Board/Pinout Guidelines. Please visit the above noted User Guide specific to your MIG design.

Virtex-5 Memory Interface Solutions

Spartan-3 Generation Memory Interface Solutions

Virtex-4 Memory Interface Solutions

Revision History
11/15/11- Updated to point to MIG documentation pages
4/6/11 - Added WP383 and XAPP868
3/1/11 - Added 7 Series Memory Interface Documentation

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34243 Xilinx MIG Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39549 MIG Virtex-6 DDR2/DDR3 - Read and Write FIFO Depths N/A N/A
34204 MIG v3.0-3.3, Virtex-6 DDR3/DDR2 - Read Leveling Stage 2 fails in hardware due to OCB Monitor issue N/A N/A
35978 Design Advisory for MIG, MPMC Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs N/A N/A
35976 Design Advisory for MIG, MPMC Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality (software/IP update required) N/A N/A
35818 Design Advisory for Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 Interfaces N/A N/A
36291 MIG, MPMC, Spartan-6 MCB - Memory failures occur on initial configuration N/A N/A
39076 MIG Virtex-6, Spartan-6 FPGA MCB - Disabling the DLL from a Micron memory DIMM N/A N/A
40876 MIG 7 Series v1.1 DDR3 SDRAM - MIG allows setting memory frequencies above data sheet specifications N/A N/A
41981 MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Addr/Cntrl Pins Should be Limited to a Single Bank N/A N/A

Actions

AR# 34263
Date Created 05/25/2010
Last Updated 03/07/2013
Status Active
Type Solution Center
IP
  • MIG
  • MIG 7 Series
  • MIG Virtex-6 and Spartan-6
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