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AR# 34264

SPI-3 Link Layer v7.1 Rev1 - Virtex-6 BRAM resource utilization in 11.4 data sheet is not accurate


The BRAM count in the data sheet is not accurate for Virtex-6 FPGA. This will be updated in the next revision of the core released in 12.1.


The correct BRAM resource utilization is shown below:

Block RAM
Tx Core (8-bit)

1 (36k BRAM)
1 (18k BRAM)

Tx Core (32-bit) 1 (36k BRAM)
2 (18k BRAM)
Rx Core (8-bit) 1 (36k BRAM)
Rx Core (32-bit) 1 (36k BRAM)
1 (18k BRAM)

AR# 34264
Date Created 03/05/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • SPI-3 Link Layer Interface, Multi-channel
  • SPI-3 Physical Layer Interface, Multi-channel