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AR# 34265

MIG Solution Center - MIG Virtex-6 and Spartan-6 Top Issues

Description

The following answer records cover current known issues as well as commonly asked questions related to MIG.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

MIG Known Issues
(XTP025) - Xilinx IP Release Notes Guide

MIG Design Advisories
(Xilinx Answer 33566)Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores

MIG Virtex-6 Top Questions
(Xilinx Answer 33607) MIG v3.2, v3.3, Virtex-6 DDR3/DDR2 - Guidelines on swapping data byte placement (RTL and UCF requirements)
(Xilinx Answer 33268) MIG Virtex-6 DDR2/DDR3 - Is it possible to combine MMCMs to save MMCM resources in multi-controller designs?
(Xilinx Answer 33137) MIG v3.1, v3.2, v3.3 Virtex-6 FPGA DDR2/DDR3 SDRAM - Why do writes on the DDR interface contain more data than requested from the user interface?

MIG Spartan-6 Top Questions
(Xilinx Answer 34150) - Spartan-6 FPGA MCB - Which unused MCB pins can be used as GPIO?
(Xilinx Answer 34055) - Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?
(Xilinx Answer 34153) - Spartan-6 FPGA MCB - Can MCB pins be swapped to help ease board layout?
(Xilinx Answer 34154) - Spartan-6 FPGA MCB - What is the REFRESH period and can it be changed?

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51287 Xilinx MIG Solution Center - Top Issues and Frequently Asked Questions (FAQ) N/A N/A

Associated Answer Records

AR# 34265
Date Created 05/25/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • MIG Virtex-6 and Spartan-6