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AR# 34266 Xilinx Virtex-6 MIG Solution Center - Design Assistant

Description

The Virtex-6 MIG Design Assistant will walk you through the recommended design flow for Virtex-6 MIG while debugging commonly encountered issues, such as simulation issues, calibration failures, and data errors. The Design Assistant will not only provide useful design and troubleshooting information, but also point you to the exact documentation you need to read to help you design efficiently with MIG.

Note: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Please first select the design phase where you have a question or are troubleshooting an issue related to your MIG design. This will ensure the MIG Design Assistant points you to the information you need to continually move forward with your design.

(Xilinx Answer 34282) Core Functionality
(Xilinx Answer 34283) Core Generation
(Xilinx Answer 34284) Simulation
(Xilinx Answer 34285) Implementation
(Xilinx Answer 34286) Hardware

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44173 Xilinx MIG Solution Center - Design Assistant N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43595 MIG Spartan-6 FPGA DDR2/DDR3 - Using CORE Generator N/A N/A
40532 MIG Spartan-6 MCB - FPGA Device support N/A N/A
40155 MIG Design Assistant - Spartan-6 MCB Supported Features N/A N/A
39549 MIG Virtex-6 DDR2/DDR3 - Read and Write FIFO Depths N/A N/A
37541 MIG Spartan-6 Memory Controller Block (MCB) Core - Data Widths N/A N/A
34323 MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output N/A N/A
34322 MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Options N/A N/A
34320 MIG 7 Series and Virtex-6 DDR2/DDR3 - Usage of User Design N/A N/A
34319 MIG 7 Series and Virtex-6 DDR2/DDR3 - Usage of Example Design N/A N/A
34318 MIG 7 Series and Virtex-6 DDR2/DDR3 - Description of Output Directory/Files N/A N/A
34316 MIG Virtex-6 DDR2/DDR3 - Supported Features N/A N/A
34315 MIG Virtex-6 DDR2/DDR3 - Supported CoreGen Options N/A N/A
34314 MIG 7 Series and Virtex-6 DDR2/DDR3 - Supported Devices N/A N/A
34286 MIG Design Assistant - Virtex-6 DDR2/DDR3 Hardware N/A N/A
34285 MIG Design Assistant - Virtex-6 Synthesis and Implementation N/A N/A
34284 MIG Design Assistant - Virtex-6 DDR2/DDR3 Simulation N/A N/A
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A
34282 MIG Design Assistant - Virtex-6 Core Functionality N/A N/A
34267 MIG v3.2-3.4 Virtex-6 DDR3 - Can banks be shared between multiple memory controllers? N/A N/A

Actions

AR# 34266
Date Created 05/25/2010
Last Updated 02/25/2013
Status Active
Type Solution Center
Devices
  • Virtex-6 SXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
IP
  • MIG
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