Mydesignis targetinga Spartan-6 LX150T device and I notice that the Placer is not using the top/bottom clock regions for slices, despite the fact that many I/O sites are placed on the top/bottom edges. It seems like this placement restriction could lead to timing issues.
How can I disable the placer behavior so that it can utilize the entire chip?
The default behavior of the Placer is to avoid using the top and bottom clock regions for designs that do not have high utilization and do not have critical paths in these areas. Although it should not be necessary, it is possible to remove thisclock region restriction by setting the following environment variable:
setenv TURNOFF_MEDUTILHEUR 1
For general information about setting ISE Design Suite environment variables, see (Xilinx Answer 11630).