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AR# 34279

Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Patches and Wrapper Source Code Updates

Description

This Answer Record is a cumulative list of patches or wrapper source code updates for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express.

Solution

The table below lists the most recent patches for each version of the core. The last entry in the table also includes an archive of older versions for reference.

For known issues about each release, see the Xilinx IP Release Notes Guide (XTP025):
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

For production silicon users, you should update to v1.5 or later using ISE 12 series software.

All ES silicon designs must use v1.3 rev 2 and ISE 12.1 or later software. The v1.4 (any version) and v1.5 cores are not supported on ES silicon.
v1.5
v1.5 Update 1
This update is needed for both Verilog and VHDL users of the x8 Gen 2 128-bit wrapper interface. See (Xilinx Answer 37207) for more information. VHDL users need to download this update after installing v1.5.1 because v1.5.1 does not include this update.
http://www.xilinx.com/txpatches/pub/applications/pci/ar37207_v6_pcie_v1_5_update1.zip

v1.5 rev 1
This patch enables VHDL file generation and VHDL testbench generation and fixes issues in the VHDL wrapper to ensure they are equivalent to the Verilog version. This is only needed if you want to enable VHDL files. Otherwise, this patch does not have to be applied. This patch is to be applied on ISE 12.1. For more information about this patch, see (Xilinx Answer 34611).
v1.4
v1.4 rev 3

This patch enables VHDL file generation and VHDL testbench generation. This is only needed if you want to enable VHDL files. Otherwise, this patch does not have to be applied. This patch is to be applied on ISE 11.5. If you are using ISE 11.4, see other patches and updates below. For more information about this patch, see (Xilinx Answer 34611).
Only use this patch if you have ISE 11.5 installed.

v1.3
v1.3 rev 2

All ES silicon designs should use this patch and ISE 12.1 or later.
This patch is includes updates in the v1.3 rev 1 patch so only this patch needs to be installed.

Patch Install Instructions
Install the patch by extracting the contents of the ".zip" archive to the root directory of the Xilinx ISE installation as pointed to by your XILINX environment variable. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

Xilinx recommends backing up the following directory of the version of the core being updated before unzipping the file. For example, for v1.5:
%XILINX%\12.1\ISE\coregen\ip\xilinx\network\com\xilinx\ip\v6_pcie_v1_5

For further information on finding the Xilinx install and using environment variable, see (Xilinx Answer 11630)

NOTE: You might be required to have a system administrator to install the patch if you do not have write permissions to the Xilinx Install directory, or cannot use the MYXILINX option.

After installing the patch and generating the core, the "v6_pcie_readme.txt" should note it has been updated. For example, v1.5 rev 1 will have: Version: 1.3 Rev 1.
Archived Patches
The patches below are older versions and should not be used any more. These are preserved to ensure customers can reference them if necessary.

Patch v1.4 rev 2
This patch was delivered natively with CORE Generator as part of the ISE 11.5 update.

Patch v1.4 rev 1:
This patch enables VHDL file generation and VHDL testbench generation. This is only needed if you want to enable VHDL files. Otherwise, this patch does not have to be applied. After installing this patch, you will still need the updates for the v1.4 core as the patch does not contain those updates. For more information about this patch, see (Xilinx Answer 34182).

Only use this patch if you have ISE 11.4 installed. This patch is superseded by the v1.4 rev 3 patch once ISE 11.5 is installed.

http://www.xilinx.com/txpatches/pub/swhelp/ise11_updates/ar34182_v6_pcie_v1_4_1.zip

Wrapper Source Updates for v1.4
This ZIP file contains two update described in these answer records. You should only use these update is you are using v1.4. The v1.4 rev 2 and rev 3 patch includes these fixes.
(Xilinx Answer 34280) - Added on 02/02/2010 - Fix for Gen 1 training problem with 100 MHz reference clock.
(Xilinx Answer 34144) - Added on 02/02/2010 - MMCO VCO Settings Update

http://www.xilinx.com/txpatches/pub/applications/pci/ar34279_v6_pcie_v1_4.zip

Patch v1.3 rev 1
This patch has been superseded by the v1.3 rev 2 patch. All customers using ES silicon should update to v1.3 rev 2 and ISE 12.1 or later.

http://www.xilinx.com/txpatches/pub/swhelp/ise12_updates/ar35422_v6_pcie_v1_3_1.zip

Wrapper Source Updates for v1.4
This is no longer needed. Use v1.3 rev 2 instead. This patch fixed the issue in:
(Xilinx Answer 34739) - Added on 03/12/2010 - MMCO VCO Settings Update

http://www.xilinx.com/txpatches/pub/applications/pci/ar34279_v6_pcie_v1_3.zip




Revision History
08/04/2010 - Added v1.5 Update 1
07/20/2010 - Fixed v1.5 link.
07/07/2010 - Fixed index tags.
07/01/2010 - Added v1.3 rev 2
05/04/2010 - Added note that v1.3 update is not needed if patch installed.
05/03/2010 - Added v1.3 rev 1 patch reference to AR 35422
03/12/2010 - Added v1.3 patch for ISE 11.5
03/08/2010 - Update for ISE 11.5 v1.4 rev 3 patch 02/02/2010 - Initial Release
AR# 34279
Date Created 02/02/2010
Last Updated 08/09/2010
Status Active
Type ??????
Devices
  • Virtex-6 LXT
IP
  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express