UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34296

11.4 Place - "ERROR:Place:1040 - Unroutable Placement! An IPAD / GTP_DUAL"

Description


I am using EDK xps_ll_temac and have configured the TEMAC to use SGMII interface. However, when I generate my design, the following errors occur:

"ERROR:Place:1040 - Unroutable Placement! An IPAD / GT component pair have been found that are not placed at a routable
IPAD / GT site pair. The IPAD component <SGMII0_RXP_0_pin> is placed at site <IPAD_X1Y33>. The corresponding GT
component
<SGMII0/SGMII0/V5HARD_SYS.I_TEMAC/SINGLE_SGMII_NOTFX.I_EMAC_TOP/GTP_dual_1000X_inst/GTP_1000X/tile0_rocketio_wrapper_
i/gtp_dual_i> is placed at site <GTP_DUAL_X0Y0>. The IPAD can route to the GT <RXP0> pin only if the load component
is placed at an offset of (-2, -2) with respect to the driver component. This placement is UNROUTABLE in PAR and
therefore, this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in
the .ucf file to demote this message to a WARNING in order to generate an NCD file. This NCD file can then be used in
FPGA Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is listed below.
These examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
< PIN "SGMII0_RXP_0_pin_IBUF.O" CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN
"SGMII0/SGMII0/V5HARD_SYS.I_TEMAC/SINGLE_SGMII_NOTFX.I_EMAC_TOP/GTP_dual_1000X_inst/GTP_1000X/
tile0_rocketio_wrapper_i/gtp_dual_i.RXP0" CLOCK_DEDICATED_ROUTE = FALSE; >"

Solution


It is likely that this issue is occurring because the pinout is using GTP 1 (TX1 and RX1) of the GTP_Dual when it should be using GTP 0 (TX0 and RX0).

Double-check the associated pinout of your GTP_Dual with UG196. If this is the case, change your pinout to use the GTP0 transceiver.
AR# 34296
Date Created 02/26/2010
Last Updated 02/22/2013
Status Active
Type General Article
Devices
  • Virtex-5 LXT
  • Virtex-5 LX
Tools
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Endpoint Block Wrapper for PCI Express
  • Ethernet 1000BASE-X PCS/PMA or SGMII
  • XPS LL TEMAC