UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3431

M1.4 MAP/PAR: BUFG is not routed properly for 3164Apc84 package.

Description

Keywords: 3100, 3k, bufg, gclk, aclk, buf, buffer

Urgency: Hot

Geneal Description:
A clock signal is locked to pin13 and connected to a bufg.
Pin 14 is also locked as an output. Signal going to P14 is
a clock signal coming out of another bufg.

P13 is not using the dedicated bufg, instead P14 is always
using it. P13 will assignment will either be ignored
and replaced by P57, or P13 will be used but ACLK (dedicated to
P57) is used.

Solution

Filing CR 103173 assigned to be fix in x1_5.
The workaround is to use ACLK or GCLK explicitly.
AR# 3431
Date Created 08/31/2007
Last Updated 10/06/2008
Status Archive
Type General Article