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AR# 34315 MIG Virtex-6 DDR2/DDR3 - Supported CoreGen Options

Description

This section of the MIG Design Assistant focuses on Supported CORE Generator Options for Virtex-6 DDR3/DDR2 designs. Below, you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

For a complete list of supported CORE Generator options for Virtex-6 DDR3/DDR2 designs please refer to the "DDR2 and DDR3 SDRAM Memory Interface Solution"=>"Getting Started"=>"Customizing and Generating the Core" and "DDR2 and DDR3 SDRAM Memory Interface Solution"=>"Getting Started"=>"Creating Virtex-6 FPGA DDR3 Memory Controller Block Design" sections in UG406: http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

If you are targeting Synplify Pro, ensure you select Synplicity in the CORE Generator Project Options. The RTL and project files generated by MIG will be different based on this selection.

Actions

AR# 34315
Date Created 05/24/2010
Last Updated 05/24/2010
Status Active
Type
Devices
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • MIG
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