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AR# 34317

MIG Virtex-6 DDR3/DDR2 - Usage of Inner Column for Address/Control Group


This section of the MIG Design Assistant focuses on the Usage of Inner Column for Address/Control Groupfor Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you're starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Address/Control Groups can only be used in inner column banks to meet the clock jitter requirements for the memory. The center banks have the shortest physical connection from the MMCM to the output pins using the performance clock path CLKPERF which provides the lowest amount of jitter. In addition, minimizing the clock jitter is critical to get the best possible read capture window as the input clock jitter at the memory is generally reflected back to the DQ outputs.

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Associated Answer Records

AR# 34317
Date Created 05/18/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
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  • MIG