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AR# 34318 MIG 7 Series and Virtex-6 DDR2/DDR3 - Description of Output Directory/Files

Description

This section of the MIG Design Assistant focuses on the output directory structure and generated files for 7 Series and Virtex-6 FPGA DDR3/DDR2 designs. Below you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

For a description of output directory/files for 7 Series and Virtex-6 DDR3/DDR2 designs, please refer to the "DDR2 and DDR3 SDRAM Memory Interface Solution > Getting Started with the CORE Generator tool > Directory Structure and File Descriptions" section of the Virtex-6 Memory Interface Solutions User Guide and in the 7 Series FPGAs Memory Interface Solutions User Guide.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34323 MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output N/A N/A
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34323 MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output N/A N/A
34266 Xilinx Virtex-6 MIG Solution Center - Design Assistant N/A N/A
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A

Actions

AR# 34318
Date Created 05/24/2010
Last Updated 10/04/2012
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Less
IP
  • MIG
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