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AR# 34323 MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Output

Description

This section of the MIG Design Assistant focuses on MIG Output for 7 Series and Virtex-6 DDR3/DDR2 designs. The MIG output includes rtl files for the MIG core, an example traffic generator, simulation testbench with the appropriate memory model instantiated, simulation and implementation script files, and a User Constraints Files (.ucf). These files allow users to quickly simulate the design to view functional behavior and create a bitfile to run the design in hardware. Please select from the below options to find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

For a description of the MIG 7 Series and Virtex-6 DDR3/DDR2 design output directory and files, please see: (Xilinx Answer 34318)- Description of Output Directory/Files

For information on the MIG 7 Series and Virtex-6 DDR3/DDR2 Example Design, please see: (Xilinx Answer 34319)- Usage of Example Design

For information on the MIG 7 Series and Virtex-6 DDR3/DDR2 User Design, please see: (Xilinx Answer 34320)- Usage of User Design

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34321 MIG 7 Series and Virtex-6 DDR2/DDR3 - Using the CORE Generator tool N/A N/A
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A
34320 MIG 7 Series and Virtex-6 DDR2/DDR3 - Usage of User Design N/A N/A
34318 MIG 7 Series and Virtex-6 DDR2/DDR3 - Description of Output Directory/Files N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34266 Xilinx Virtex-6 MIG Solution Center - Design Assistant N/A N/A
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A
34318 MIG 7 Series and Virtex-6 DDR2/DDR3 - Description of Output Directory/Files N/A N/A
34319 MIG 7 Series and Virtex-6 DDR2/DDR3 - Usage of Example Design N/A N/A
34320 MIG 7 Series and Virtex-6 DDR2/DDR3 - Usage of User Design N/A N/A
34321 MIG 7 Series and Virtex-6 DDR2/DDR3 - Using the CORE Generator tool N/A N/A

Actions

AR# 34323
Date Created 05/25/2010
Last Updated 10/04/2012
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Less
IP
  • MIG
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