This section of the MIG Design Assistant focuses on the JEDEC Specification as it applies to the MIG Virtex-6 DDR3/DDR2 FPGA designs. Below you will find information related to your specific question.
NOTE: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The MIG Virtex-6 DDR2/DDR3 controller completes a JEDEC standard compliant initialization sequence. The simulation testbench skips the initial 200 s delay to speed up simulation times. In hardware, this requirement is observed.The controller adheres to all timing parameters as defined by the JEDEC standards.
The following links provide additional detail regarding the MIG controller and various requirements regarding the JEDEC standards: