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AR# 34341 Spartan-6 FPGA Integrated Endpoint Block v1.2 for PCI Express - Simulation failure when using ISE 11.5 to simulate a v1.2 core generated in ISE Design Suite 11.3 or 11.4, in 11.5

Description

When using ISE 11.5 to simulate a v1.2 wrapper generated in ISE 11.4 or 11.3 software, simulation will fail with the following error message:

Attribute Syntax Error : The calculation of VCO frequency=500.000000 Mhz. This exceeds the permitted VCO frequency range of 600.000000 Mhz to 1600.000000 Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range.

Solution

An update is available in (Xilinx Answer 34615); download the ZIP file titled "ar34615_s6_pcie_v1_2.zip" from the Answer Record.

The ZIP file contains a file titled pcie_clocking_v6.v[hd] which contains new settings for the MMCM VCO parameters. Place this file in your generated core's simulation/dsport directory. The directory is:

<corename>/simulation/dsport/pcie_clocking_v6.v[hd]

Note that this ZIP file is cumulative and may contain fixes for other problems as described in (Xilinx Answer 34615).

Revision History
02/14/2011- Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34615 Spartan-6 FPGA Integrated Block Wrapper for PCI Express - Patches and Wrapper Source Code Updates N/A N/A
33277 Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.3 N/A N/A

Actions

AR# 34341
Date Created 02/14/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 11.4
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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