I have an ISE tools design that contains an EDK submodule. I have designed a custom testbench that instantiates the top level module and would like to run a simulation for the complete ISE/EDK design.
However, when the simulation is initiated from the ISE tool, the processor data that is supposed to be initialized in the block RAM does not seem to be in the block RAM model. When the processor accesses information from its internal block RAM, nothing is returned.
This issue does not occur when the EDK system is standalone.
Additional HDL code needs to be added to the testbench so that the block RAM is initialized. The following HDL statements need to be included so that the initialization happens:
For Verilog (Anywhere between "module" and "end module"):
// Data initialization
For VHDL (After "end architecture"):
configuration system_tb_conf of system_tb is
for all : system
use configuration work.system_conf;
For the system_init.v that is generated by EDK's Simulation Generator (simgen), the design hierachy will now have changed. Please update the content of the file with the appropriate hierachical names.
You can refer to the testbench that EDK generated as a guide to creating the custom ISE tool testbench.