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AR# 34352 11.4 Virtex-6 MAP - Constant optimization of LUT6_2 inputs mishandled leading to errors

Description

My design fails in MAP with the following error which says that the I0 pin of this LUT6_2 instance is undriven due to trimming. I have examined the logic involved and it appears that the logic driving this pin is constant (rather than undriven). Should MAP not optimize the LUT6_2 to account for this without an error?

"ERROR:MapLib - LUT6_2 symbol "skt00/tx_core/ID_S_3b4a94a4_3fb34892_
E.ID_S_78bb3df7_65a80dc7_E.ID_S_7053e8b7_5b00d9ba_E_3_lut6_2[8]"
(output signal=skt00/tx_core/ID_S_3b4a94a4_3fb34892_E.ID_S_78bb3df7_
65a80dc7_E.ID_S_7053e8b7_5b00d9ba_E_3[7]) has an equation that uses
input pin I0 which no longer has a connected signal. Please ensure that all the
pins used in the equation for this LUT have signals that are not trimmed (see
Section 5 of the Map Report File for details on which signals were trimmed)."

Solution

There is a known problem in ISE Design Suite 11.x where MAP incorrectly reports this trimming error when constant optimization is occurring. This problem has been fixed for ISE Design Suite 12.1. Meanwhile, the error can be avoided by setting the following environment variable:

Linux
setenv XIL_MAP_NO_IS_LUT6_2_VALID 1

Windows
SET XIL_MAP_NO_IS_LUT6_2_VALID=1
For general information about setting ISE Design Suite environment variables, see (Xilinx Answer 11630).

Actions

AR# 34352
Date Created 02/09/2010
Last Updated 02/18/2010
Status Active
Type
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-6 CXT
  • More
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
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