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AR# 34355

MIG Virtex-6 DDR3 - JEDEC Specification - ZQ Calibration

Description

This section of the MIG Design Assistant focuses on the ZQ Calibration defined by the JEDEC Specification, as it applies to the MIG Virtex-6 FPGA DDR3 designs.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The MIG Virtex-6 FPGA DDR3 design includes ZQ Short (ZQCS) and ZQ Long (ZQCL) Calibration commands that adhere to the DDR3 JEDEC Standard. The ZQ Calibration Command is discussed in section 5.5 of JEDEC Spec JESD79-3 DDR3 SDRAM Standard.

The ZQ Calibration command allows the on die termination (ODT) to be calibrated at regular intervals to account for variations across voltage and temperature. The logic that controls the sending of these commands is part of the controller (not the phy layer) in the module bank_common.v/vhd. The parameter Tzqcs determines the refresh rate of how often the ZQ Calibration command is sent to the memory.

(Xilinx Answer 33957) - If I run the MIG v3.3 design through simulation or in hardware, the ZQCL command is observed during initialization, but not during normal operation.

Linked Answer Records

Associated Answer Records

AR# 34355
Date Created 05/20/2010
Last Updated 09/25/2012
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • MIG