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AR# 34356

LogiCORE IP Video On Screen Display (OSD) v1.0 - Why is the vfbc_wd_clk output always low?

Description

Why is the vfbc_wd_clk output always low?

Why do I receive the following XST message when synthesizing the Video On Screen Display pcore as part of my EDK project?

WARNING:Xst:1305 - Ouput <vfbc_wd_clk> is never assigned, Tied to value 0. (line 3833 of the synthesis report).

Solution

This is a known issue with the v1.0 Video On Screen Display core, that is scheduled to be fixed in the next release.

You can work around this issue by connecting the input clock of the write VDMA (Video DMA) to the core clock (clk) being used by the Video On Screen Display.

For a detailed list of LogiCORE IP Video On Screen Display Release Notes and Known Issues, see (Xilinx Answer 33257)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33257 LogiCORE IP Video On Screen Display (OSD) - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33257 LogiCORE IP Video On Screen Display (OSD) - Release Notes and Known Issues N/A N/A
AR# 34356
Date Created 02/09/2010
Last Updated 08/05/2014
Status Active
Type General Article
IP
  • On-Screen Display