Why is the vfbc_wd_clk output always low?
Why do I receive the following XST message when synthesizing the Video On Screen Display pcore as part of my EDK project?
This is a known issue with the v1.0 Video On Screen Display core, that is scheduled to be fixed in the next release.
You can work around this issue by connecting the input clock of the write VDMA (Video DMA) to the core clock (clk) being used by the Video On Screen Display.
For a detailed list of LogiCORE IP Video On Screen Display Release Notes and Known Issues, see (Xilinx Answer 33257)