We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34360

11.4 Spartan-6 Place - Clock Placer prints false BUFH error "ERROR:Place:1225 - The BUFH component ..."


Map printed the following Place errors for my design:

"Phase 6.30 Global Clock Region Assignment
ERROR:Place:1225 - The BUFH component <XYZ > is locked to site < BUFH_X3Y1 >. There is a conflict with BUFG component < XYZ> placed at site < BUFGMUX_X3Y15 >. The BUFG and BUFH sites share a clock spine in the given clock region. The location constraints on the BUFH or BUFG must be moved to resolve this conflict.

ERROR:Place - INTERNAL ERROR: Could not get a single region clock site for compXYZ in region 1.
ERROR:Place - INTERNAL ERROR: Could not place clockXYZ in region 1."

However, it continued processing after the error. What does this mean and can I use the resulting NCD file?


The clock placer is known to print false errors of this type. The problem has already been fixed for ISE 12.1. Meanwhile, the error can be ignored since it does not stop processing. Since the false error does lead to Map passing a non-zero return code, Project Navigator GUI processing ceases. Project Navigator users need to use the "Force Process Up To Date" feature to bypass this issue.
AR# 34360
Date Created 02/09/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4