The design is HDL based and includes a ChipScope Core being inserted. The Constraints Editor shows the ChipScope constraints in the GUI.
When "Validate Clocks" is clicked, ISE 11.x series crashes with the following message:
"A Xilinx Application has encountered an unexpected error. It is recommended that you save any unsaved work in the event that this condition persists. For further assistance, please consult the Answers Database and other online resources at http://support.xilinx.com"
When "Validate Clocks" is clicked, ISE 12.x adds a duplicate constraint on J_CLK. This would repeat for the number of times I perform"Validate Clocks".
How can I resolve this issue?
The ChipScope constraints are automatically included in the netlist starting with the 11.x series. So, the ChipScope constraint can be disabledin the Constraints Editor GUI, and you can perform "Validate Clocks".
The issue in 12.x series is under investigation and is scheduled to be fixed in a future release of the software.