This section of the MIG Design Assistant focuses on the Reset Pin defined by the JEDEC Specification as it applies to the MIG Virtex-6 and 7 series FPGA DDR3 designs.
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The Reset Pin is a new feature in DDR3 Memories and is defined in section 3.3 of the JEDEC specification JESD79-3 DDR3 SDRAM Standard.
The Reset Pin is used during the memory initialization procedure and is required. As a result, it is not possible to omit this signal from the pin-out. Please see the "Design Guidelines" section of the Virtex-6 Memory Interface Solutions User Guide or the 7 Series Memory Interface Solutions User Guide.
(Xilinx Answer 47232) MIG 7 Series - DDR3L Reset Guidelines