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AR# 34370

MIG DDR3 - JEDEC Specification; DDR3 SDRAM Reset Pin

Description

This section of the MIG Design Assistant focuses on the Reset Pin defined by the JEDEC Specification as it applies to the MIG Virtex-6 and 7 series FPGA DDR3 designs.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The Reset Pin is a new feature in DDR3 Memories and is defined in section 3.3 of the JEDEC specification JESD79-3 DDR3 SDRAM Standard.

The Reset Pin is used during the memory initialization procedure and is required. As a result, it is not possible to omit this signal from the pin-out. Please see the "Design Guidelines" section of the Virtex-6 Memory Interface Solutions User Guide or the 7 Series Memory Interface Solutions User Guide.

Additional Information
(Xilinx Answer 47232) MIG 7 Series - DDR3L Reset Guidelines

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51684 MIG 7 Series DDR2/DDR3 - JEDEC Specification N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
47232 MIG 7 Series DDR3L - RESET# recommendations to meet JEDEC standard requirements N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34330 MIG Virtex-6 DDR2/DDR3 - JEDEC Specification N/A N/A
AR# 34370
Date Created 05/21/2010
Last Updated 09/10/2012
Status Active
Type Solution Center
Devices
  • Virtex-6
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
  • MIG Virtex-6 and Spartan-6