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AR# 34386

MIG 7 Series and Virtex-6 DDR2/DDR3 - Verify UCF and Update Design and UCF

Description

Starting with MIG 3.4, available with ISE tools 12.1, Verify UCF and Update Design and UCF is available for Virtex-6 DDR2/DDR3 designs. The feature is also included for all MIG 7 Series designs. This flow allows users to verify changes made to a MIG output UCF, create a new design based on the verified UCF changes, and generate an updated version of the MIG core.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Verify UCF

Users might want to modify pin locations specified in the output MIG UCF to ease board layout.The Verify UCF and Update Design and UCF features allow users to input the original "mig.prj" file and the modified ".ucf" file, and then verify all locations constraints against the "mig.prj" file. For information on how to use this tool and information on errors generated by the tool, see the "Verify UCF and Update Design and UCF Rules" section in Virtex-6 Memory Interface Solutions User Guide (UG406) and in the "Verify Pin Changes and Update Design" section in the 7 Series FPGAs Memory Interface Solutions User Guide.

For detailed information on the Pin-out and Banking Requirements, see:

(Xilinx Answer 34308) - MIG Virtex-6 DDR3/DDR2 - Verify pin-out/banking requirements are met
(Xilinx Answer 51317) - MIG 7 Series DDR2/DDR3 - Verify pin-out/banking requirements are met

For information on using the Fixed Pin-out tool, which allows users with a custom pin-out to generate the core in one step, see (Xilinx Answer 34388).

Update Design and UCF

This portion of the Verify UCF and Update Design and UCF tool allows users to generate an updated design based on the input UCF and "mig.prj" files.The UCF is first verified in the Verify stage and then the tool generates an updated design.The MIG tool updates the design from the version noted in the "mig.prj" to the version of MIG launched. This allows users the ability to easily update a MIG core to the newest version by simply inputting their "mig.prj" and UCF files (with this, users do not have to manually select all core options and regenerate their core to the latest version).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A

Associated Answer Records

AR# 34386
Date Created 05/18/2010
Last Updated 10/04/2012
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Less
IP
  • MIG