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AR# 34390

MIG Virtex-6 DDR3/DDR2 - Usage of Inner/Outer Columns for Data Group

Description

The Virtex-6 DDR3/DDR2 MIG design allows Data groups (DQ/DQS signals) to be placed in either inner or outer I/O columns. The Data group banks must be placed within 3 "H-Row" (horizontal row) banks due to the design's use of regional clock resources.

This section of the MIG Design Assistant focuses on theuse of Inner/Outer Columns for Data Group for Virtex-6 DDR3/DDR2 designs.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

For design frequencies of 400 MHz and below, Data Groups can be used in both inner and outer column banks that reside within three H-Row banks.

For design frequencies of 400 MHz and higher, only Inner Column banks are allowed for Data group selection.

The lower frequency for the outer column is due to additional jitter added on the performance path clock driving I/Os in the outer columns. The performance path clock is a low jitter output clock from the MMCM that goes directly to I/O. The MMCMs are located between the two inner I/O columns. Additional jitter will be added when a performance path clock drives outer column I/O. For full details on the design's use of the performance path clock, please see the Core Architecture > PHY section of UG406.

For information on design requirements for the Address/Control group within the inner column, please see (Xilinx Answer 34317).

For general Pin-out and Banking Requirements, please see (Xilinx Answer 34308).

Linked Answer Records

Associated Answer Records

AR# 34390
Date Created 05/18/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG