The Virtex-6 DDR3/DDR2 MIG design allows Data groups (DQ/DQS signals) to be placed in either inner or outer I/O columns. The Data group banks must be placed within 3 "H-Row" (horizontal row) banks due to the design's use of regional clock resources.
This section of the MIG Design Assistant focuses on theuse of Inner/Outer Columns for Data Group for Virtex-6 DDR3/DDR2 designs.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243)
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