Table 1-8: "PCIe Edge Connector Connections" on page 33 ofthe ML605 Hardware User Guide v1.2.1, January 21, 2010 (UG534) shows the following GTXE placement for ML605:
However, the correct placement locations are as follows:
When generating the "Virtex-6 Integrated Block for PCI Express" from within CORE Generator and choosing the ML605 as the selected development board, the UCF that is created is correct and no modifications need to be made.
ML605 Hardware User Guide (UG534) v1.3 includes this fix.
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