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AR# 34405

ML605 Hardware User Guide (UG534) - GTXE1 Package placement is incorrectly shown on page 33

Description

Table 1-8: "PCIe Edge Connector Connections" on page 33 ofthe ML605 Hardware User Guide v1.2.1, January 21, 2010 (UG534) shows the following GTXE placement for ML605:

GTXE1_X0Y15
GTXE1_X0Y14
GTXE1_X0Y13
GTXE1_X0Y11
GTXE1_X0Y10
GTXE1_X0Y9
GTXE1_X0Y8
GTXE1_X0Y7

However, the correct placement locations are as follows:

GTXE1_X0Y15
GTXE1_X0Y14
GTXE1_X0Y13
GTXE1_X0Y12
GTXE1_X0Y11
GTXE1_X0Y10
GTXE1_X0Y9
GTXE1_X0Y8

Solution

When generating the "Virtex-6 Integrated Block for PCI Express" from within CORE Generator and choosing the ML605 as the selected development board, the UCF that is created is correct and no modifications need to be made.

ML605 Hardware User Guide (UG534) v1.3 includes this fix.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34836 Virtex-6 FPGA ML605 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 34405
Date Created 02/16/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Virtex-6 FPGA GTX Transceiver Wizard
Boards & Kits
  • Virtex-6 FPGA Connectivity Kit
  • Virtex-6 FPGA ML605 Evaluation Kit