There is a need for the level translator when using 3.3V SPI flash with Virtex-6 FPGA. So, we can consider any of the industry standard Level translators for 3.3Vto 2.5V. When translators are used the configuration speed is reduced. So, to calculate the maximum CCLK to be applied during Master SPI configurationwe need three parameters. They are as follows:
a) For any of the selected industry standard Level translators we need to consider the propagation delay for 2.5 to 3.3V translation. For our Example we will consider it to be 4 ns.
b)Thesecond parameter to be considered is Din setup time for the Master SPI configuration in the Virtex-6 FPGA, which is 2.5 ns. This info can be found in the data sheet in the configuration switching characteristics section.
c) The third parameter is Clock Low to Output Valid for the SPI flash. This parameter value is generally provided in the third-party SPI flash data sheets. Considering one of the industry standards forSPI flash, this value is 8 ns.
So, in general, to calculate the maximum clock frequency of the CCLK to be set in Virtex-6 for SPI configuration is:
CCLK(freq) = 1/ (2 * (Clock Low to Output Valid of SPI flash + propagation delay of level translator + setup time(TSPIDCC/TSPIDCCD) for the FPGA during SPI flash configuration))
CCLK(freq) = 1/(2 *(4 + 8 + 2.5)ns)) ~ 34 MHz
So, for the example parameters the maximum configuration clock (CCLK) can be for Master SPI configuration is around 34 MHz.
Please note here the board trace delay is not considered for the FPGA to Level translator and Level translator to SPI flash.