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AR# 34414



Are the SCL and SDA pins required when interfacing to an RDIMM device with the Virtex-6 MIG controller?

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The SCL and SDA pins are used to access the SPD (Serial Presence Detect) EEPROM located on the DIMM. These pins are not used in the current memory interface designs. They are reserved for future use.

These pins can be used for other purposes if the system designer determines that access to the SPD is not required. The DDR3 RDIMM interface uses the default values for the register on the RDIMM. This is sufficient for the current set of RDIMM parts that this interface supports. If an RDIMM is used that requires specific register programming information to be extracted from the SPD and this register programming information is not available statically on the datasheet, then the SCL and SDA pins will be required. This is not expected to be common.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35812 MIG Virtex-6 DDR2/DDR3 - FPGA Device support N/A N/A
34314 MIG 7 Series and Virtex-6 DDR2/DDR3 - Supported Devices N/A N/A
AR# 34414
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • MIG
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