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AR# 34432

Virtex-6 FPGA Connectivity Kit and Targeted Reference Design (TRD) - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the Virtex-6 FPGA Connectivity Kit and its Targeted Reference Design.

The nature of this content is to help you avoid running into issues when performing intended operations with the kit.

The Virtex-6 FPGA Connectivity Kit v1.0 includes the following components:

Software:

  • ISE Design Suite
  • Fedora 10 LiveCD (32-bit kernel version 2.6.27)
Hardware:
  • ML605 board with an XC6VLX240T-1-FF1156 FPGA
  • Vita 57.1 FMC daughter card with one CX4, two SATA, and eight SMA connectors

Solution

The following versions of Virtex-6 FPGA Connectivity Kit Targeted Reference Design are available:

V6 Connectivity TRD

Silicon

ISE

PCIe

XAUI

Memory Controller(MIG)

v 1.0

CES

11.4

v 1.3

v 9.1

v 3.3

v 1.1

CES

12.1

v 1.3 + rev 1 patch

v 9.1

v 3.4

v 1.1

Production

12.1

v 1.5

v 9.2

v 3.4

v 1.2

CES

12.2

v 1.3 + rev 2 patch

v 9.1

v 3.5

v 1.2

Production

12.2

v 1.5

v 9.2

v 3.5

v 1.3

CES

12.3

v 1.3 + rev 2 patch

v 9.1

v 3.6

v 1.3

Production

12.3

v 1.6

v 9.2

v 3.6

v 1.0 with AXI4 protocol support

Production

12.3

v 2.1

v 9.2

v 3.6

v 1.4

CES

12.4

v 1.3 + rev 2 patch

v 9.1

v 3.6.1

v 1.4

Production

12.4

v 1.6

v 9.2

v 3.6.1

v 1.1 with AXI4 protocol support

Production

12.4

v 2.2

v 9.2

v 3.6.1

v 1.2 with AXI4 protocol support

Production

13.1

v 2.3

v 10.1

v 3.7

v 1.3 with AXI4 protocol support

Production

13.2

v 2.4

v 10.1

v 3.8

v 1.4 with AXI4 protocol support

Production

13.3

v 2.4

v 10.1

v 3.9

v 1.5 with AXI4 protocol support

Production

13.4

v 2.5

v 10.2

v 3.91



To understand which version of the silicon you have, please see (Xilinx Answer 37579).

For all design versions prior to 13.1, the Virtex-6 GTX Transceiver - Delay Aligner Work-around might be required.

For more information, refer to (Xilinx Answer 39430), (Xilinx Answer 39456), and (Xilinx Answer 39492).

For all design versions before 13.2, the TRCE/Timing Analyzer tools have not correctly analyzed the Virtex-6 36Kb block RAM (RAMB36E1),18Kb RAM(RAMB18E1), and 18Kb FIFO (FIFO18E1) control signals when used in SDP, TDP, or ECC modes.

This can potentially result in unreported setup and hold time violations. 

The unreported violations might result in read and write errors. 

For more information, refer to (Xilinx Answer 42444).

Virtex-6 FPGA Connectivity Kit TRD v1.0 for ISE 11.4 with CES Silicon

  • Silicon
    • The kit ships with CES v1.1 silicon. Refer to ES Errata for any further information.
  • IP Cores
  • Targeted Reference Design
  • Targeted Reference Design User Guide (UG372)
    • Block RAM Utilization numbers in (UG372) do not match the numbers reported by MAP or PAR processes (Xilinx Answer 34651).
    • In the Register Descriptions section of (UG372) the register value for Completed Byte Count should be 0x001C instead of 0x001D.
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.

ISE 11.5 is not supported. Do not upgrade to 11.5. Check (Xilinx Answer 34432) for updates.

  • TRD was simulated with ModelSim 6.4b and ModelSim Questa 6.5a.
  • ISIM support is not available.
  • The supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.

Virtex-6 FPGA Connectivity Kit TRD v1.1 for ISE 12.1 with CES Silicon

  • Silicon
    • The kit ships with CES v1.1 silicon. Refer to ES Errata for any further information.
  • IP Cores
    • PCIe: The TRD uses version 1.3 rev1 of Virtex-6 Integrated Block Wrapper for PCI Express.
      Only version 1.3 of the IP works reliably with ES parts.
      Do not update to version 1.4 (Xilinx Answer 34033).
       
    • PCIe: The PCIe link can fail to come up, or might come up at x1 only on a cold boot (Xilinx Answer 35426).
      If this occurs, a warm reboot should fix the issue.
       
    • XAUI: The TRD incorporates fixes in (Xilinx Answer 33488) and (Xilinx Answer 33649) related to XAUI.
      Only version 9.1 of the IP has been verified with ES parts.
      Do not update to later versions.
       
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
       
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Targeted Reference Design User Guide (UG372).
    • In the Register Descriptions section of (UG372), the register value for Completed Byte Count should be 0x001C instead of 0x001D.
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • Project Navigator - Constraints from the UCF file(s) are being ignored (Xilinx Answer 35677).
    • TRD was simulated with ModelSim 6.4b and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.

Virtex-6 FPGA Connectivity Kit TRD v1.1 for ISE 12.1 with Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Targeted Reference Design User Guide (UG372).
    • In the Register Descriptions section of (UG372), the register value for Completed Byte Count should be 0x001C instead of 0x001D.
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • Project Navigator - Constraints from the UCF file(s) are being ignored (Xilinx Answer 35677).
    • TRD was simulated with ModelSim 6.4b and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The supported Linux version is provided on the Fedora10Linux Live CD included in the kit.

Virtex-6 FPGA Connectivity Kit TRD v1.2 for ISE 12.2 with CES Silicon

  • Silicon
    • The kit ships with CES v1.1 silicon. Refer to ES Errata for any further information.
  • IP Cores
    • PCIe: The TRD uses version 1.3 rev2 of Virtex-6 Integrated Block Wrapper for PCI Express.
      Only version 1.3 of the IP works reliably with ES parts.
      Do not update to version 1.4 (Xilinx Answer 34033).
    • PCIe: Virtex-6 FPGA Integrated Block Wrapper v1.3 rev 2 - Updated GT settings (Xilinx Answer 36677).
    • XAUI: The TRD incorporates fixes in (Xilinx Answer 33488) and (Xilinx Answer 33649) related to XAUI.
      Only version 9.1 of the IP has been verified with ES parts.
      Do not update to later versions.
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Targeted Reference Design User Guide (UG372).
    • In the Register Descriptions section of (UG372), the register value for Completed Byte Count should be 0x001C instead of 0x001D.
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.4b and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The Supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.

Virtex-6 FPGA Connectivity Kit TRD v1.2 for ISE 12.2 with Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • PCIe: Virtex-6 FPGA Integrated Block Wrapper v1.5 - Updated GT settings (Xilinx Answer 36677).
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Targeted Reference Design User Guide (UG372)
    • In the Register Descriptions section of (UG372), the register value for Completed Byte Count should be 0x001C instead of 0x001D.
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.4b and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The Supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.

Virtex-6 FPGA Connectivity Kit TRD v1.3 for ISE 12.3 with CES Silicon

  • Silicon
    • The kit ships with CES v1.1 silicon. Refer to ES Errata for any further information.
  • IP Cores
    • PCIe: The TRD uses version 1.3 of Virtex-6 Integrated Block Wrapper for PCI Express. Only version 1.3 of the IP works reliably with ES parts. Consequently, do not update to version 1.4 (Xilinx Answer 34033).
    • XAUI: The TRD incorporates fixes in (Xilinx Answer 33488) and (Xilinx Answer 33649) related to XAUI. Only version 9.1 of the IP has been verified with ES parts. Consequently, do not update to later versions.
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.5c and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The supported Linux version is provided on the Fedora 10Linux Live CD included in the kit.

Virtex-6 FPGA Connectivity Kit TRD v1.3 for ISE 12.3 with Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.5c and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The Supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.

Virtex-6 FPGA Connectivity Kit TRD v1.0 with AXI4 Protocol for ISE 12.3 on Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.5c and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The Supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.

Virtex-6 Connectivity Kit TRD v1.4 for ISE 12.4 with CES Silicon

  • Silicon
    • The kit ships with CES v1.1 silicon. Refer to ES Errata for any further information.
  • IP Cores
    • PCIe: The TRD uses version 1.3 of Virtex-6 Integrated Block Wrapper for PCI Express. Only version 1.3 of the IP works reliably with ES parts. Consequently, do not update to version 1.4 (Xilinx Answer 34033).
    • XAUI: The TRD incorporates fixes in (Xilinx Answer 33488) and (Xilinx Answer 33649) related to XAUI. Only version 9.1 of the IP has been verified with ES parts. Because of this, do not update to later versions.
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.5c and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The Supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.

Virtex-6 Connectivity Kit TRD v1.4 for ISE 12.4 with Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.5c and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The supported Linux version is provided on the Fedora 10Linux Live CD included in the kit.

Virtex-6 FPGA Connectivity Kit TRD v1.1 with AXI4 Protocol support for ISE 12.4 on Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
  • Tools
    • TRD source files only available in Verilog
    • TRD has not been synthesized with Synplicity
    • TRD was simulated with ModelSim 6.5c and ModelSim Questa 6.5a.
    • ISIM support is not available.
    • The supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.

Virtex-6 Connectivity Kit TRD v1.2 with AXI4 Protocol support for ISE 13.1 on Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
    • Timing Issues (Xilinx Answer 34650).
    • DDR3 fails to initialize (Xilinx Answer 34655).
    • PCIe will only train to Gen1 (Xilinx Answer 34657).
    • This version and later versions of the TRD will no longer support Project Navigator flows.
    • This version of the design is not backward compatible with earlier version of the driver.
      If the current version of the design and an older version of the driver is used, the performance numbers in the GUI will always be zero.
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.6d and ModelSim Questa 6.6c.
    • ISIM support is not available.
    • The supported Linux version is provided on the Fedora10Linux Live CD included in the kit.

Virtex-6 Connectivity Kit TRD v1.3 with AXI4 Protocol support for ISE 13.2 on Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
    • Timing Issues (Xilinx Answer 34650).
    • DDR3 fails to initialize (Xilinx Answer 34655).
    • PCIe will only train to Gen1 (Xilinx Answer 34657).
    • This version and later versions of the TRD will no longer support Project Navigator flows.
    • This version of the design is not backward compatible with earlier version of the driver.
      If the current version of the design and an older version of the driver is used, the performance numbers in the GUI will always be zero.
    • PlanAhead Flow on Windows for the TRD released in 13.2 does not meet timing out of the box. Solution provided in (Xilinx Answer 43097).
    • When testing the TRD on the Linux machine, the Application GUI might not load successfully. Solution provided in (Xilinx Answer 44362)
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.6d and ModelSim Questa 6.6d.
    • ISIM support is not available.
    • The supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.
    • The Windows driver has been tested and works on Windows XP-32bit systems (English, SP3). Support on Windows 7, 64-bit systems and other flavors of Windows XP is not yet available.

      If the windows driver source code is modified, the drivers need to be recompiled.
      Appendix D in the TRD user guide (UG379) provides steps on Windows driver compilation using the Windows Device Driver kit (WDK).
      WDK provides two build environments - Free build and Checked build.
      There are no issues with the Free build.
      With the checked build, the drivers compile and load successfully, but when the GUI is invoked and a test is run, the system might hang or freeze.

Virtex-6 Connectivity Kit TRD v1.4 with AXI4 Protocol support for ISE 13.3 on Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
    • Timing Issues (Xilinx Answer 34650).
    • DDR3 fails to initialize (Xilinx Answer 34655).
    • PCIe will only train to Gen1 (Xilinx Answer 34657).
    • This version and later versions of the TRD will no longer support Project Navigator flows.
    • This version of the design is not backward compatible with earlier version of the driver.
      If the current version of the design and an older version of the driver is used, the performance numbers in the GUI will always be zero.
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.6d and ModelSim Questa 6.6d.
    • ISIM support is not available.
    • The supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.
    • The Windows driver has been tested and works on Windows XP-32bit systems (English, SP3). Support on Windows 7, 64-bit systems and other versions of Windows XP is not yet available.

Virtex-6 Connectivity Kit TRD v1.5 with AXI4 Protocol support for ISE 13.4 on Production Silicon

  • Silicon
    • The kit ships with production silicon.
  • IP Cores
    • Memory Controller (MIG): The TRD Uses Custom MIG Files (Xilinx Answer 34652).
    • Northwest Logic Release Notes included in TRD.
  • Targeted Reference Design
    • Timing Issues (Xilinx Answer 34650).
    • DDR3 fails to initialize (Xilinx Answer 34655).
    • PCIe will only train to Gen1 (Xilinx Answer 34657).
    • This version and later versions of the TRD will no longer support Project Navigator flows.
    • This version of the design is not backward compatible with earlier version of the driver.
      If the current version of the design and an older version of the driver is used, the performance numbers in the GUI will always be zero.
  • Tools
    • TRD source files only available in Verilog.
    • TRD has not been synthesized with Synplicity.
    • TRD was simulated with ModelSim 6.6d and ModelSim Questa 6.6d.
    • ISIM support is not available.
    • The supported Linux version is provided on the Fedora 10 Linux Live CD included in the kit.
    • The Windows driver has been tested and works on Windows XP-32bit systems (English, SP3). Support on Windows 7, 64-bit systems and other versions of Windows XP is not yet available.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43750 Xilinx Boards and Kits Solution Center - Top Issues N/A N/A

Child Answer Records

Associated Answer Records

AR# 34432
Date Created 03/15/2010
Last Updated 01/26/2015
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
Boards & Kits
  • Virtex-6 FPGA Connectivity Kit