MIG v3.3 Virtex-6 DDR3 - ODT not asserted properly during initial write leveling and timing calibration causes calibration to fail

AR#	34445	Search For Another Answer
Topic	MIG
Last Updated	06/09/2011
Status	Active

Description

MIG 3.3 and earlier Virtex-6 DDR3 designs may not properly assert ODT during initial write leveling and timing calibration. ODT timing following completion of calibration and initialization is correct.  This issue will be seen as a failure to complete calibration (phy_init_done never goes high).

This issue only affects DDR3 designs using ODT where RTT_WR is OFF.  This can be determined by looking at the top-level RTT_WR parameter.  The Example Design top-level module is example_top.v/.vhd and the User Design top-level is core_name.v/.vhd.
RTT_WR = "OFF"

If this parameter is set to any other configuration, the design is not affected by this issue.

Solution

To work around this issue:
1. Open the phy_init.v module located in the MIG output 'rtl/phy' directory. 

2. Locate the following code fragment in phy_init.v:

// Assert ODT when: (1) Write Leveling, (2) Issuing Write command
// Timing of ODT is not particularly precise (i.e. does not turn
// on right before write data, and turn off immediately after
// write is finished), but it doesn't have to be
generate
if (nSLOTS == 1) begin
always @(posedge clk)
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3"))begin
phy_odt0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_odt1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
else if ((((RTT_WR != "OFF") && (DRAM_TYPE == "DDR3"))
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& ((wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE_READ))) begin
phy_odt0 <= #TCQ phy_tmp_odt0_r;
phy_odt1 <= #TCQ phy_tmp_odt1_r;
end else begin
phy_odt0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_odt1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end

3. Make the following change (highlighted in bold):
// Assert ODT when: (1) Write Leveling, (2) Issuing Write command
// Timing of ODT is not particularly precise (i.e. does not turn
// on right before write data, and turn off immediately after
// write is finished), but it doesn't have to be
generate
if (nSLOTS == 1) begin
always @(posedge clk)
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3"))begin
phy_odt0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_odt1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& ((wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
(init_state_r == INIT_RDLVL_STG2_WRITE) ||
(init_state_r == INIT_RDLVL_STG2_WRITE_READ))) begin
phy_odt0 <= #TCQ phy_tmp_odt0_r;
phy_odt1 <= #TCQ phy_tmp_odt1_r;
end else begin
phy_odt0 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
phy_odt1 <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
 

This issue will be resolved in MIG v3.4 which will be released with ISE 12.1 software.