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Spartan-6 FPGA Integrated Endpoint Block v1.2 rev 1 for PCI Express - Simulation never finishes when simulating a v1.2 rev 1 core generated in ISE Design Suite 11.5

AR# 34451

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Topic PCIe
Last Updated 03/08/2010
Status Active
Description

When I simulate a design using the Spartan-6 FPGA Integrated Endpoint Block v1.2 rev 1 for PCI Express downstream port model generated in ISE Design Suite 11.5, the simulation never completes.

Solution

An update is available in (Xilinx Answer 34615); download the ZIP file titled "ar34615_s6_pcie_v1_2.zip" from the Answer Record.

The ZIP file contains a file titled "pcie_clocking_v6.v[hd]" which corrects this problem. Place this file in your generated core's simulation/dsport directory.

The directory is:  /simulation/dsport/pcie_clocking_v6.v[hd]

Note that this ZIP file is cumulative and can contain fixes for other problems as described in (Xilinx Answer 34615).

Revision History
03/08/2010 - Initial Release

Applies To

Devices

  • Spartan-6 LXT

IP

  • Endpoint Block Wrapper for PCI Express
 
 
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