No, the EDK PLBv46_PCIe core is limited to 2.5Gb/s.
The Virtex-6 PCIe core used in the design is PCIe v2.0 compliant. The bridge design uses this core for the Virtex-6 FPGA implementation and identifies itself on the PCIe bus as v2.0 compliant. Both 5Gb/s and 2.5 Gb/s speeds are supported in PCIe v2.0. The bridge design is limited to 2.5 Gb/s. The document for v4.04 of the plbv46_pcie has a note added to indicate this.