To correct for voltage and temperature drift over time, the phase detector dynamically locks the phase of the internally generated capture clocks so that they are 90 degrees offset from the DQS[0] signal. The circuit monitors the phase on only DQS[0] as the VT affect on all DQS signalsare nearly identical. As the phase moves, the phase of the capture clocks are adjusted using the phase shift of the MMCM.
In order to monitor the phase on DQS[0] within the phase detector, reads must be present on the DDR bus. The memory controller is responsible for issuing "periodic reads". If reads are already present on the bus, as requested by the user interface, the insertion of a periodic read is not required. The phase detector will look at the phase on DQS during any read. If, however, there is a period with no read activity, the memory controller issues a periodic read every 1 us. This 1 us period is set by the tPRDI timer within the controller. When it expires, a dummy read is sent. The tPRDI parameter is set in the memc_ui_top module. This interval for periodic reads has been tested in all Xilinx characterization and is the only interval supported by Xilinx.
The phase detector logic is contained in the phy_pd.v/vhd module.
For a detailed description on the Phase Detector Logic, refer to "DDR2 and DDR3 SDRAM Memory Interface Solution"=>"Core Architecture"=>"PHY" section in
UG406. Figure 1-55: Phase Detector Timing Diagram shows how the circuit monitors for DQS shift over voltage/temperature drift and then shifts the cpt_clk (using the phase shift on the MMCM) based on any DQS shift. The phase detector is continuously watching DQS phase during reads.
The MIG design disables the periodic reads for DDR2 designs running at or below 200 MHz.For more information, see
(Xilinx Answer 34476).
For more information on the usage of DQS, see
(Xilinx Answer 35113).