My design is failing during placement with a message about an unroutable DCM pin named PROGCLK. The design has no such connection in the source. Why does this error occur?
"ERROR:Place:1194 - Unroutable Placement! A BUFGMUX that drives a DCM on the PROGCLK pin is not placed at a routable site. The BUFGMUX component
<BL_VIDEO_GRAPHICS_G_VIDEO_GRAPHICS_U_VIDEO_GRAPHICS/bl_video_camera_u_LS_LVDS_camera/bl_LVDS_RX_inst_HS_RX/rxclk_bufauto> is placed at site <BUFGMUX_X2Y9>. The DCM component
<BL_VIDEO_GRAPHICS_G_VIDEO_GRAPHICS_U_VIDEO_GRAPHICS/bl_video_camera_u_LS_LVDS_camera/bl_LVDS_RX_inst_HS_RX/dcm_rxclk a> is placed at <DCM_X0Y1>. The BUFGMUX can drive the DCM.PROGCLK pin if the BUFGMUX is in TOP half of the chip. This placement is UNROUTABLE in PAR and therefore, this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD file. This NCD file can then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
<PIN "BL_VIDEO_GRAPHICS_G_VIDEO_GRAPHICS_U_VIDEO_GRAPHICS/bl_video_camera_u_LS_LVDS_camera/bl_LVDS_RX_inst_HS_RX/rxclk_buf auto.O" CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN "BL_VIDEO_GRAPHICS_G_VIDEO_GRAPHICS_U_VIDEO_GRAPHICS/bl_video_camera_u_LS_LVDS_camera/bl_LVDS_RX_inst_HS_RX/
dcm_rxclka.PSCLK" CLOCK_DEDICATED_ROUTE = FALSE; >"
This message is incorrectly reporting a problem with the PROGCLK pin when the actual problem is with the PSCLK pin of the DCM. The message is otherwise correct that when a DCM's PSCLK is driven by a BUFG, the BUFG must be placed in one of the upper 8 BUFG sites; from page 60 of:
Clock input to variable phase shifter, clocked on rising edge. When using a global clock buffer, only the upper eight BUFGMUXs can drive PSCLK: BUFGMUX_X2Y1, BUFGMUX_X2Y2, BUFGMUX_X2Y3, BUFGMUX_X2Y4, BUFGMUX_X3Y5, BUFGMUX_X3Y6, BUFGMUX_X3Y7, and BUFGMUX_X3Y8.
This problem can be avoided by using a LOC constraint to lock the BUFG component to one of of the upper BUFG sites.
Example UCF syntax:
INST "BUFG_Name" LOC = BUFGMUX_X2Y1;