We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34483

11 EDK - Simulation takes a long time before jumping to main ()


To simulate a packet transmission design, I increased the size of the internal block RAM to 32 KB for my simulation project and instantiated a larger character array of maximum Ethernet frame size, which is 1500 bytes. When I run the simulation, the program takes a long time before actually jumping to main (). I did not have this problem before (when the block RAM was smaller).


The longer simulation time is due to the clearing of the BSS section.

The reason is that all global variables, heap, and stack go into the BSS section. Since they are uninitialized data, the startup function (crtinit) needs to clear the BSS section first before jumping to main ().Each loop in the BSS section can clear 4 bytes of data and each loop takes about 5 processor clock cycles.

In this case, if there is a global character array of 1500 bytes, it should take about 1500/4*5 ~ 2000 cycles to complete clearing the BSS section, which is seen in the long simulation time.

AR# 34483
Date 12/15/2012
Status Active
Type General Article
  • EDK - 11.4
Page Bookmarked