We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34486

Spartan-6 Clocking Wizard - DCM allowed input frequency incorrect


The maximum allowed frequency of the DCM in the ISE 11.4 Clocking Wizard is too high.The Clocking Wizard permits double the actual allowed input frequency.

This issue is resolved in the ISE12.1 Clocking Wizard.


The ISE 11.4 Clocking Wizard assumes that the DIVBY2 feature (which divides the input to the DCM by 2 before the DCM input pin)is beingused. Therefore, it allows 2X the maximum input clock frequency (500 MHz while the maximum input frequency is 250 MHz).

This "Divide By 2" feature is available and it can be used, but the Architecture Wizard mistakenly assumes it is always used.This assumption is removed in ISE12.1 Architecture Wizard, so the input frequency range is correct.

The workaround for ISE 11.4 software is to not violate the input clock frequencies in the Spartan-6 FPGA Data Sheet. The preferred workaround is to update to the most current software version. For the allowed input frequency range of the DCM, see the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics (DS162):

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46790 Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems N/A N/A
AR# 34486
Date Created 02/25/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Clock Generator
  • Digital Clock Manager (DCM) Module