We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34491

SPI-4.2 v9.3 - Static Alignment could intermittently fail to go in-frame


An issue has been seen where the parallel ISERDES output misaligns following a core reset, resulting in the core failing to train and go in-frame. This condition can occur only when the ISERDES sees a glitch in its clock during reset and when it is configured for static alignment. This rarely happens and can be avoided if the ISERDES is reset along with the core. To exit out of this undesirable condition, re-configure the device (power-cycle).

This applies to any static alignment sink core v9.3 or earlier.


This issue is scheduled to be fixed in the next release of the core (12.1). If you have run into this issue, please contact Xilinx Technical Support.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33313 SPI-4.2 v9.3, v9.3 Rev1 and v9.3 Rev2 - Release Notes and Known Issues for ISE 11.3/11.4/11.5 N/A N/A
AR# 34491
Date Created 02/25/2010
Last Updated 05/23/2014
Status Archive
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • Less
  • SPI-4 Phase 2 Interface Solutions