I have a design that runs through synthesis and implementation without errors. However, when I attempt to generate a bitstream (run Bitgen), I encounter errors in Bitgen DRC associated with my input pads:
PhysDesignRules:10 - The network <enc3_cha_in> is completely unrouted.
How can I resolve this error?
These errors can occur if you attempt to generate a bitstream for a design with no buffers added to the input or output ports. These ports will not be routable. PAR will report warnings on this port as follows:
WARNING:Par:289 - The signal enc3_cha_in has no driver. PAR will not attempt to route this signal.
This situation can occur if the design was synthesized without I/O buffers. For XST, this can be done if the "Add I/O Buffers (-iobuf)" property is disabled.
To resolve this issue, make sure the design has instantiated input buffers, or buffers are inferred by the synthesis tool.