UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34508

11.1 EDK, MPMC v5.00.a - "ERROR:Pack:946 - The I/O component "DDR_Clk" has an illegal IOSTANDARD..."

Description

When using MPMC in a Spartan-3 device to target DDR designs, the following error occurs:

"ERROR:Pack:946 - The I/O component "fpga_0_DDR_SDRAM_DDR_Clk_pin" has an illegal IOSTANDARD value. Components of type IOB do not support IOSTANDARD DIFF_SSTL2_II. Please correct the IOSTANDARD property value."

How do I resolve this issue?

Solution

Change the IOSTANDARD to SSTL in the system.ucf file:

NET "ddr_mpmc_DDR_Clk_pin[*]" IOSTANDARD = SSTL2_II;
NET "ddr_mpmc_DDR_Clk_n_pin[*]" IOSTANDARD = SSTL2_II;

This issue is fixed in MPMCv6.00.a, to be released in EDK 12.1.
AR# 34508
Date Created 03/02/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-3
Tools
  • EDK - 11.1
  • EDK - 11.2
  • EDK - 11.3
  • EDK - 11.4
IP
  • Multi-Port Memory Controller (MPMC)