We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34520

11.4 EDK, MPMC v5.04.a - VFBC command FIFO reset causes spurious commands or shifting video


When I use the VFBC, there are occasional extra commands being output from VFBC to external memory after a command FIFO reset. Addtional data from those transactions occur and cause horizontally shifting video.

How do I resolve this issue?


Issuing a command reset can cause the FIFO empty signal to be low for one clock cycle after reset is de-asserted due to the async nature of the command FIFO. If the cycle where the empty flag is low occurs during the clock cycle during which the command request clock enable is high, then the VFBC new command controller incorrectly issues a new command.

A patch for 11.4 is available in (Xilinx Answer34504).

This issue is fixed in MPMC v6.00.a, to be released in EDK 12.1.

AR# 34520
Date Created 03/02/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • More
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • EDK - 10.1 sp3
  • EDK - 11.1
  • EDK - 11.2
  • More
  • EDK - 11.3
  • EDK - 11.4
  • Less
  • Multi-Port Memory Controller (MPMC)