The SPI-3 Link Layer v7.1 Rev1 and earlier cores have the potential for internal block RAM collisions due to the restriction regarding READ_FIRST mode and asynchronous clocking as documented in the "Spartan-6 FPGA Block RAM Resources User's Guide". This issue might not be reported in simulation and could cause the core to fail in hardware. As such, the core should not be used for production at this time.
For more information, see (Xilinx Answer 34533).