UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34526

SPI-3 Link Layer v7.1 Rev1 - Spartan-6 FPGA core should not be used in production due to potential block RAM memory collision

Description

The SPI-3 Link Layer v7.1 Rev1 and earlier cores have the potential for internal block RAM collisions due to the restriction regarding READ_FIRST mode and asynchronous clocking as documented in the "Spartan-6 FPGA Block RAM Resources User's Guide". This issue might not be reported in simulation and could cause the core to fail in hardware. As such, the core should not be used for production at this time.

For more information, see (Xilinx Answer 34533).

Solution

This issue is scheduled to be fixed in the next release of the core in ISE Design Suite 12.1.
AR# 34526
Date Created 03/03/2010
Last Updated 05/23/2014
Status Archive
Type General Article