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AR# 34527

SPI-3 Link Layer Core - Some designs may fail timing

Description

A small percentage of designs containing the SPI-3 Link Layer Core could fail to meet timing as the DCM phase shifts provided in the Example Design do not cover all differences in the user board layout and core configuration. These failures are reported in PAR or Trace with errors similar to the following:

"WARNING:Par:62 - Your design did not meet timing."

Solution

In these cases, you can achieve timing closure for the design by modifying the DCM PHASE_SHIFT values in the UCF file. You will need to determine the ideal phase shift for your system; once this value is found, the constraints will meet timing.
AR# 34527
Date Created 03/03/2010
Last Updated 05/23/2014
Status Archive
Type General Article