Design Assistant

Xilinx Solution Center for PCI Express - Design Assistant

The Design Assistant for PCIe walks you through the recommended design flow for PCIe while debugging commonly encountered issues such as simulation and hardware problems. The Design Assistant not only provides useful design and troubleshoot information but also points you to the exact documentation you need to read to help you design efficiently with PCIe.

NOTE: This answer record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Please first select the design phase where you have a question or are troubleshooting an issue related to your PCIe design. This will ensure the Design Assistant for PCI Express points you to the information you need to continually move forward with your design.

(Xilinx Answer 36062) - Core Functionality or Protocol
(Xilinx Answer 35107) - Simulation
(Xilinx Answer 36174) - Synthesis or Implementation
(Xilinx Answer 34085) - Hardware

Revision History
09/04/2012 - Minor update
08/13/2010 - Initial release

Answer Number	Answer Title	Version Found	Version Resolved
35722	Design Assistant for PCI Express - How to add a PCI Express cores to Project Navigator?	N/A	N/A

Virtex-5 Endpoint Block Plus for PCI Express - Value for cfg_interrupt_mmenable signal

Virtex-5 PCIe block plus User Guide (UG341) describes only "000b" encoding for cfg_interrupt_mmenable signal. This AR contains the description of other encoding values for this cfg_interrupt_mmenable signal.

For encoding values other than "000b", please refer to 6.8.1.3 Message Control for MSI of the PCI Local BUS SPECIFICATION, REV. 3.0.

Encoding	# of Vectors Allocated
000	1
001	2
010	4
011	8
100	16
101	32
110	Reserved
111	Reserved

Revision History:
4/3/2012 - Initial Release

Documentation

Xilinx Solution Center for PCI Express - Documentation

This answer record includes links to documentation for the solutions of PCI Express.

NOTE: This answer record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Solution Center is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

7 Series FPGAs
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_7series-integrated-block.htm

Virtex-6 FPGAs
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_v6pciexpressendpointblock.htm

Spartan-6 FPGAs
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_s6pciexpressendpointblock.htm

Virtex-5 FPGAs
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_v5pciexpressblockplus.htm

Endpoint Pipe
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci_do-di-pcie-pipe.htm

AXI Bridge for PCI Express
http://www.xilinx.com/support/documentation/ipembedprocess_peripheralpci_axi-pcie.htm

PLBv46 Bridge for PCI Express
http://www.xilinx.com/support/documentation/ipembedprocess_peripheralpci_plbv46pcie.htm

PCIe Design Advisory Answer Records

(Xilinx Answer 33775) - Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express
(Xilinx Answer 33776) - Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express
(Xilinx Answer 33580) - Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express

Release Notes
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Boards and Kits

Virtex-6 ML605
http://www.xilinx.com/support/documentation/ml605.htm

Spartan-6 SP605
http://www.xilinx.com/support/documentation/sp605.htm

Virtex-5 ML555
http://www.xilinx.com/support/documentation/ml555.htm

Targeted Reference Designs and Connectivity Kits

Virtex-6
http://www.xilinx.com/support/documentation/virtex-6_fpga_connectivity_kit.htm

Spartan-6
http://www.xilinx.com/support/documentation/spartan-6_fpga_connectivity_kit.htm

White Papers

Understanding Performance of PCI Express Systems
http://www.xilinx.com/support/documentation/white_papers/wp350.pdf

Application Notes

XAPP859: Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs: DDR2 SDRAM DMA Initiator Demonstration Platform
http://www.xilinx.com/support/documentation/application_notes/xapp859.pdf

XAPP1002: Using ChipScope Pro to Debug Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE
http://www.xilinx.com/support/documentation/application_notes/xapp1002.pdf

XAPP 1022: Using the Memory Endpoint Test Driver (MET) with the Programmed Input/Output Example Design for PCI Express Endpoint Cores
http://www.xilinx.com/support/documentation/application_notes/xapp1022.pdf

XAPP 1052: Bus Master DMA Performance Demonstration Reference Design for the Xilinx Endpoint PCI Express Solutions
http://www.xilinx.com/support/documentation/application_notes/xapp1052.pdf

Design Advisories

Design Advisories for 7-Series/Virtex-6/Spartan-6 Integrated Block and Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

For the Solution Center for PCI Express, refer to (Xilinx Answer 34536).

(Xilinx Answer 33775) - Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express
(Xilinx Answer 33776) - Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express
(Xilinx Answer 33580) - Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express

NOTE: There is no design advisory for 7 Series FPGAs Integrated Block for PCI Express.

Revision History
09/03/2012 - Initial release

Top Issues

Xilinx Solution Center for PCI Express - Top Issues

The following answer records cover current known issues as well as commonly asked questions related to PCI Express.

NOTE: This answer record is part of the Xilinx PCI Express Solution Center (Xilinx Answer 34536). The Xilinx PCI Express Solution Center is available to address all questions related to PCI Express. Whether you are starting a new design with PCI Express or troubleshooting a problem, use the PCI Express Solution Center to guide you to the right information.

Known Issues
(Xilinx Answer 40469) - 7 Series FPGAs Integrated Block for PCI Express - Release Notes and Known Issues for All Versions
(Xilinx Answer 47441) - Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions
(Xilinx Answer 45723) - Virtex-6 FPGA Integrated Block for PCI Express v2.x - Release Notes and Known Issues for all AXI Interface Versions
(Xilinx Answer 40446) - Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express - Release Notes and Known Issues
(Xilinx Answer 45702) - Spartan-6 FPGA Integrated Block for PCI Express v2.x - Release Notes and Known Issues for all AXI Interface versions
(Xilinx Answer 37938) - Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues
(Xilinx Answer 42760) - Endpoint Block Plus Wrapper v1.15 for PCI Express - Release Notes and Known Issues for ISE Design Suite 13.2

Top Issues
N/A

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