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AR# 34538 Xilinx Solution Center for PCI Express - Design Assistant

Description

The Design Assistant for PCIe walks you through the recommended design flow for PCIe while debugging commonly encountered issues such as simulation and hardware problems. The Design Assistant not only provides useful design and troubleshoot information but also points you to the exact documentation you need to read to help you design efficiently with PCIe.

NOTE: This answer record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

Please first select the design phase where you have a question or are troubleshooting an issue related to your PCIe design. This will ensure the Design Assistant for PCI Express points you to the information you need to continually move forward with your design.

(Xilinx Answer 36062) - Core Functionality or Protocol
(Xilinx Answer 35107) - Simulation
(Xilinx Answer 36174) - Synthesis or Implementation
(Xilinx Answer 34085) - Hardware

Revision History
09/04/2012 - Minor update
08/13/2010 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34536 Xilinx Solution Center for PCI Express N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
35722 Design Assistant for PCI Express - How to add a PCI Express cores to Project Navigator? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40310 Design Assistant for PCI Express - What is a prefetchable bit? N/A N/A
40309 Design Assistant for PCI Express - How do you change the Device-ID without regenerating and re-implementing the core in a Virtex-6 device? N/A N/A
39523 Design Assistant for PCI Express - How do I know if the MMCM and GTX PLL are locked? N/A N/A
39522 Design Assistant for PCI Express - How do I know if the link is trained when using the Virtex-6 Integrated Block? N/A N/A
38988 Design Assistant for PCI Express - How can I force a card to train to a smaller link width? How do I tape off lanes? N/A N/A
38548 Design Assistant for PCI Express - Simulation Traffic Questions N/A N/A
38447 Design Assistant for PCI Express - Memory reads result in 0xFFFFFFFF N/A N/A
38064 Design Assistant for PCI Express - What happens when there are multiple errors in a TLP N/A N/A
37973 Design Assistant for PCI Express - Virtex-6 Integrated Block "ERROR:Place:1224 - Component-"/pcie_clocking_i/mmcm_adv_i"cannot find any feasible target location during placement" N/A N/A
37947 Design Assistant for PCI Express - Virtex-6 FPGA Integrated Block Wrapper "ERROR:ConstraintSystem:59 - Constraint " N/A N/A
37817 Design Assistant for PCI Express - How does a Gen 1 endpoint handle the reserved bits in the TS1/TS2 ordered sets that are used in Gen 2? N/A N/A
37752 Design Assistant for PCI Express - TLPs are corrupted in simulation N/A N/A
37517 Design Assistant for PCI Express - Is it necessary to use only the recommended GTP/GTX locations in the User Guide? N/A N/A
37497 Design Assistant for PCI Express - What should the Target Link Speed register in the Link Control 2 Register be set to? N/A N/A
37472 Design Assistant for PCI Express - How to read packets on the Integrated Block for PCI Express's memory (or MIM) interface N/A N/A
37406 Design Assistant for PCI Express - How to enumerate the endpoint when FPGA is configured after enumeration. N/A N/A
37180 Design Assistant for PCI Express - How is the core configured to have Extended Tag Field Support? N/A N/A
37063 Design Assistant for PCI Express - Are there any drivers available from Xilinx for PCI Express? N/A N/A
37042 Design Assistant for PCI Express - Is 128-bit interface maintained when x8 Gen2 comes up in Gen1 speed? N/A N/A
37007 Design Assistant for PCI Express - Unsupported request bit not set when cfg_err_posted_n is deasserted and cfg_err_ur_n is asserted N/A N/A
36829 Design Assistant for PCI Express - Bus Master Enable, Memory, and IO enable bits must be set for TLPs to be transmitted or Received N/A N/A
36750 Design Assistant for PCI Express - TLPs are not getting passed to the user application N/A N/A
36749 Design Assistant for PCI Express - Simulation Questions Regarding Transaction Layer Traffic N/A N/A
36633 Design Assistant for PCI Express - How can I know the values of the BARs after configuration? N/A N/A
36627 Design Assistant for PCI Express - Why Are Interrupts Not Transmitted N/A N/A
36596 Design Assistant for PCI Express - What is the difference between MAX_READ_REQUEST_SIZE and MAX_PAYLOAD_SIZE? N/A N/A
36595 Design Assistant for PCI Express - Can the User Application implement capabilities in the PCI Legacy or PCIe Extended Configuration Space? N/A N/A
36593 Design Assistant for PCI Express - How Can I Check the Negotiated Link Width and Link Speed After Link Training? N/A N/A
36591 Design Assistant for PCI Express - Why do completions for a string of memory reads not come back in the same order? N/A N/A
36589 Design Assistant for PCI Express - How do I disable the "Enable Relaxed Ordering" bit (bit 4) in the device control register? N/A N/A
36325 Design Assistant for PCI Express - How to Disable ASPM? N/A N/A
36215 Design Assistant for PCI Express - Why does reading of BAR register return all zeroes? N/A N/A
36209 Design Assistant for PCI Express - Why are no completions returned when reading or writing the configuration space? N/A N/A
36208 Design Assistant for PCI Express - Simulation Questions Regarding Configuration Traffic N/A N/A
36207 Design Assistant for PCI Express - Simulation Set-Up and Licensing Questions N/A N/A
36174 Design Assistant for PCI Express - Start here for questions regarding Synthesis or Implementation N/A N/A
36137 Design Assistant for PCI Express - trn_reset_n (user_reset_out for AXI) is deasserting, but trn_lnk_up_n (user_lnk_up_n for AXI) is not asserting N/A N/A
36075 Design Assistant for PCI Express - 128-bit interface with packet straddling N/A N/A
36063 Design Assistant for PCI Express - Why is a NAK sent on a Previously ACKed Packet? N/A N/A
36062 Design Assistant for PCI Express - Start here with questions about core functionality or protocol N/A N/A
35913 Design Assistant for PCI Express - Why does a single memory read request result in multiple completions? N/A N/A
35748 Design Assistant for PCI Express - Incorrect use of trn_trem_n could cause malformed TLPs to get transferred N/A N/A
35722 Design Assistant for PCI Express - How to add a PCI Express cores to Project Navigator? N/A N/A
35212 Design Assistant for PCI Express - How to capture Endpoint Block Plus Wrapper internal signals using ChipScope Inserter? N/A N/A
35107 Design Assistant for PCI Express - Simulation Debug N/A N/A
35034 Design Assistant for PCI Express - Completion Timeouts Cause the System to Freeze N/A N/A
35033 Design Assistant for PCI Express - Device is recognized by system, but problems occur N/A N/A
35000 Design Assistant for PCI Express - What happens if the power if the FPGA is re-configured, power is removed, or card removed during normal operation of the link N/A N/A
34894 Design Assistant for PCI Express - Using trn_reset_n to debug link training issues N/A N/A
34873 Design Assistant for PCI Express - Debugging System Recognition and Link Training Issues Using trn_lnk_up_n and trn_reset_n N/A N/A
34871 Design Assistant for PCI Express - Using JTAG to Configure the Device N/A N/A
34800 Design Assistant for PCI Express - Problems Associated with FPGA Configuration N/A N/A
34735 Design Assistant for PCI Express - Do VHDL customers need a mixed language license to simulate the integrated block and tranceiver models N/A N/A
34085 Design Assistant for PCI Express - Hardware Debug N/A N/A
34536 Xilinx Solution Center for PCI Express N/A N/A
33251 Design Assistant for PCI Express - Application Note xapp859 Design Does Not Return Completion for Memory Requests with Non-zero Attribute Field N/A N/A
34248 Design Assistant for PCI Express - MSI interrupt is not received at the host N/A N/A
34260 Design Assistant for PCI Express - trn_terr_drop_n Asserted when Transmitting a Valid Packet N/A N/A
36594 Design Assistant for PCI Express - How do I configure the core in order to use MSI or Legacy Interrupt? N/A N/A
34806 Design Assistant for PCI Express - Software that Displays PCI Express Devices In System N/A N/A
34777 Design Assistant for PCI Express - Device not recognized by system N/A N/A
47109 Virtex-5 Endpoint Block Plus for PCI Express - Value for cfg_interrupt_mmenable signal N/A N/A

Actions

AR# 34538
Date Created 08/06/2010
Last Updated 02/15/2013
Status Active
Type Solution Center
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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