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AR# 34543

MIG Virtex-6 DDR2/DDR3 - DQS I/O Placement

Description

The MIG Virtex-6 DDR2/DDR3 design uses an internally generated clock to capture the data on DQ during reads. In previous MIG designs (i.e., Virtex-5 DDR2), the DQS strobe was used to capture data.Since DQS is not used to capture data, does it have to be LOCed to a Clock Capable I/O (CCIO)?

NOTE:This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

DQS does not need to be LOCed to a CCIO site in the Virtex-6 design. It only needs to be LOCed to a p/n General Purpose I/O (GPIO) pair. The internally generated clocks (CPT and RSYNC) instead use clocking resources, and therefore require CCIO.

To view the PHY clocking structure for the Virtex-6 DDR2/DDR3 MIG design, see the PHY Clocking Architecture Figure in theVirtex-6 FPGA Memory Interface Solutions User Guide (UG406): http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

For more information on the Design/Layout Guidelines for this design, please see:


While the design does not capture data using DQS, it does monitor the phase of DQS during reads to account for any phase shift due to voltage/temperature changes. If the phase varies, the data capture clock phase is adjusted using the MMCM Phase Shift.

    Linked Answer Records

    Associated Answer Records

    AR# 34543
    Date Created 05/19/2010
    Last Updated 12/15/2012
    Status Active
    Type General Article
    Devices
    • Virtex-6 CXT
    • Virtex-6 HXT
    • Virtex-6 LX
    • More
    • Virtex-6 LXT
    • Virtex-6 SXT
    • Less
    IP
    • MIG