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AR# 34544

MIG Virtex-6 DDR2/DDR3 - Board Layout

Description

This section of the MIG Design Assistant focuses on Board Layout Guidelines for the Virtex-6 DDR3/DDR2 designs. Please select from the below options to find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The Virtex-6 DDR2/DDR3 Design requires specific board layout rules be followed in order for the design to behave correctly in hardware. The following Answer Records provide detailed information on the board layout requirements. Information can also be found in the DDR2 and DDR3 Memory Interface Solution > Design Guidelines section of The Virtex-6 Memory Interface Solutions User Guide.

On top of following these rules, it is strongly recommended users run SI Simulations using IBIS Models to verify signal integrity:

If after verifying these rules have been followed and errors are still seen in hardware, please refer back to the main Hardware section of this Design Assistant to look into Pin-out/Banking Requirements and Hardware Debug.

    Linked Answer Records

    Child Answer Records

    Answer Number Answer Title Version Found Version Resolved
    34557 MIG Virtex-6 and 7 Series DDR3 - Fly-by Topology Requirements N/A N/A
    34569 MIG - Simultaneously Switching Noise (SSN) Calculation N/A N/A

    Associated Answer Records

    AR# 34544
    Date Created 05/19/2010
    Last Updated 08/27/2012
    Status Active
    Type Solution Center
    Devices
    • Virtex-6 CXT
    • Virtex-6 HXT
    • Virtex-6 LX
    • More
    • Virtex-6 LXT
    • Virtex-6 SXT
    • Less
    IP
    • MIG